Hebbian plasticity in parallel synaptic pathways: A circuit mechanism for systems memory consolidation
Fig 6
Mathematical analysis of the hierarchical consolidation network.
(A) The mathematical analysis is performed for a network consisting of N + 1 input and N + 1 output layers. All output layers (except output layer 0) weight the input from the previous layer with a factor α and the input via the shortcut pathway with a factor 1 − α, to ensure that activity does not rise as increasingly many pathways converge onto the output layers. Input layer i is hence connected to output layer i through a shortcut connection with weight matrix (1 − α)Wi (except for the bottom-most layers i = 0, for which no factor 1 − α is required). All connections between input layers are set to the identity matrix I, and all connections between output layers are set to αI, for notational simplicity in the derivations. The math can be generalized to arbitrary connection matrices, as long as the network is linear. Each connection introduces a synaptic delay of D. The multi-synaptic pathway from input layer i to output layer i via shortcut connection j ≠ i has a total delay of (2(i − j) + 1) ⋅ D, so the difference in delays between the pathway through shortcut i and shortcut j is Dij = 2(i − j) ⋅ D. (B) The similarity Oi of the weight matrix W0 (in which memory traces are initially stored) and the shortcut connection Wi as a function of the time elapsed after storage (colored lines), and their maximum (black line). Simulations shown for D = 2 ms, α = 0.8, ηi = 2−i and STDP time constant τSTDP = 40 ms.