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Hard real-time closed-loop electrophysiology with the Real-Time eXperiment Interface (RTXI)

Fig 2

System architecture.

The bottom block depicts the hardware layer with which RTXI interfaces. RTXI is capable of interfacing with DAQs using either PCI/PCIe, USB, or Ethernet interfaces (see Compatible hardware for more information). Hard RT communication with hardware devices is achieved through Analogy, a set of drivers within the Xenomai framework. The top block of the diagram illustrates the core architecture of RTXI. On each cycle of the RT period, the RT Thread wakes up, acquires new data, executes instructions defined within the hard RT function of both core and user modules (see Custom modules and Application Programming Interface (API)), outputs data to the DAQ, and returns to sleep (idle). Transmission of data to/from different modules is handled by the IO class. When the RT Thread is idle, resources are made available to other system applications and functions. The GUI and Data Storage Threads continuously run with a static period to provide a stable balance between hard RT performance and handling of user input, updating of visualizations, and data storage.

Fig 2

doi: https://doi.org/10.1371/journal.pcbi.1005430.g002