https://orcid.org/0000-0001-9069-7865
Figures
Abstract
Quantum computing leverages quantum mechanics to perform complex computations efficiently, yet its practical implementation is hindered by hardware-software interdependence and quantum state instability. This paper advances lightweight FPGA-based quantum emulation by incorporating a universal quantum gate set, including parameterized Phase gates and the CNOT gate, to support comprehensive quantum protocol emulation on FPGA hardware. The FPGA platform used for synthesis is Artix-7. The proposed emulator is validated through simulations of quantum circuits, including Bell States, the Deutsch algorithm, Superdense coding, Grover’s search, and BB84 QKD, with results benchmarked against IBM’s noiseless quantum simulator. Utilizing FPGA’s customizable parallelism and energy efficiency, this framework offers a resource-efficient, reliable platform for developing and testing quantum algorithms.
Citation: Zahra A, Khalid M, Riaz N, Waheed S, Mujahid U, Najam-ul-Islam M (2026) FPGA-based emulation framework for two-qubit quantum computation: Design, implementation, and validation. PLoS One 21(8): e0356172. https://doi.org/10.1371/journal.pone.0356172
Editor: Zeheng Wang, Commonwealth Scientific and Industrial Research Organisation, AUSTRALIA
Received: November 28, 2025; Accepted: July 30, 2026; Published: August 24, 2026
Copyright: © 2026 Zahra et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Data Availability: The Source codes are available at via https://github.com/Arfeen983/FPGA-Based-Emulation-Framework-for-Two-Qubit-Quantum-Computation and https://www.protocols.io/view/fpga-based-emulation-framework-for-two-qubit-quant-dm6gp4bqpgzp/v2.
Funding: The author(s) received no specific funding for this work.
Competing interests: The authors have declared that no competing interests exist.
1 Introduction
In 1980, Richard Feynman and Paul Benioff presented the idea of a Quantum Computer, i.e., a hardware system based on the principles of quantum mechanics. Unlike classical computers, which operate on binary logic, this technology leverages the laws of quantum physics, allowing the system to perform powerful operations and execute certain computations efficiently.
In the present information era, Quantum Information Technology (QIT) is a field of interest for businesses, investors, and nations, as it offers increased computational power and precision in various application areas, including sensing, information security, drug discovery, optimization, and telecommunication. Core disciplines in Quantum Computing (QC) are quantum platform and algorithm design. Theoretical work on quantum algorithm design began in the latter half of the 20 century with algorithms such as Deutsch’s, Shor’s, and Grover’s, and has since evolved to include concepts like variational quantum eigensolvers, quantum approximate optimization, and Quantum Machine Learning (QML) [6–8]. While quantum algorithms have matured over time, the creation of practical execution platforms has historically been constrained by the complex interdependence of hardware and software, as well as the fundamental challenge of maintaining stable quantum states. Over the past decade, however, technological advances have enabled the construction of devices capable of deliberately manipulating nature at its fundamental quantum-mechanical level. These advances in quantum hardware have, in turn, motivated renewed interest in near-term algorithmic applications. The technologies used in the development of quantum computing hardware architecture are summarized in Table 1. Since quantum computing is both capital-intensive and strategically important, access to this technology is primarily restricted to multinational enterprises and technologically advanced economies. Organizations such as Google, Amazon, and D-Wave are at the forefront of investment. Currently, the most extensive system is reported by IBM, featuring 1,121 qubits, i.e., the quantum analog of a classical bit [9,10].
This limitation has given rise to a parallel line of research focused on emulating quantum computing using classical devices. The primary advantage of this approach lies in providing a controlled environment for exploring quantum systems, thereby mitigating the challenges of noise, decoherence, and high error rates. However, this comes at the expense of an exponential increase in computational resources with each additional qubit. These emulation platforms enable reliable, repeatable simulations, allowing for effective development, testing, and refinement of quantum algorithms before they are executed on actual hardware.
1.1 Motivation
Quantum emulators have been developed on various platforms, including Graphics Processing Units (GPUs), Central Processing Units (CPUs), and Field-Programmable Gate Arrays (FPGAs), providing platforms for executing quantum algorithms. In contrast to CPUs and GPUs, FPGAs offer the potential of customizable parallelism, energy efficiency, and flexible hardware configuration [11], making them an enabling technology for a resource-efficient yet accurate quantum emulator.
In 2021, Khalid et al. introduced a generalized, lightweight FPGA-based emulation architecture capable of simulating quantum superposition [12]. The proposed framework was synthesized on Spartan-3, keeping in view its focus on low computational cost. Given the accuracy of the BB84 emulation results demonstrated in that work, extending the framework to incorporate the full set of primary quantum gates, particularly the CNOT gate, is a notable research direction.
1.2 Contributions
The list of contributions presented in the paper is as follows:
- Extension of the reference FPGA-based quantum emulation framework by completing the universal set of quantum gates through the proposed Phase and CNOT gate architectures.
- Validation of the proposed emulator through the simulation of representative quantum circuits, including Bell States, the Deutsch algorithm, Grover’s Search, BB84 QKD, and the parallel execution of multiple independent 2-qubit Superdense Coding circuits to demonstrate the scalability of the proposed framework.
- Functional benchmarking of the proposed emulator against IBM Aer Simulator and IBM Quantum Hardware.
The proposed architectures are designed on Artix-7 in contrast to Spartan-3, i.e., the platform used by the baseline framework. This board is chosen to provide the required logic density and on-chip memory needed to instantiate and manage the emulated quantum circuits within the Finite State Machine (FSM) driven model.
1.3 Paper organization
This paper is structured as follows: Section 2 comprehensively reviews related work, exploring existing quantum simulation frameworks and their limitations to contextualize the proposed solution. Section 3 details the proposed FPGA emulator’s system architecture, while section 4 describes the implementation and theoretical benchmarking of quantum algorithms, validating their execution against expected outcomes. Section 5 presents the performance analysis, evaluating the emulator’s efficacy compared to other platforms, i.e., the IBM Quantum platform. Finally, the paper is concluded in Section 6.
2 Related work
The related work on QC emulation can be broadly categorized into two dimensions:
- The mathematical fundamentals underlying quantum phenomena.
- The existing literature on emulation architectures and design.
The subsequent subsections address these topics in sequence.
2.1 Fundamentals of quantum computing
Quantum analog of a classical bit is a qubit. While classical computers use the transistor theory to represent a binary bit, QC utilizes nanoparticles to hold information in the form of spin, i.e., an intrinsic quantum property of elementary particles. The mathematical abstraction of this physical property is a unit vector expressed as a linear combination of two orthogonal basis states in a two-dimensional complex Hilbert space. Mathematical representation of a qubit, i.e., an elementary particle spin, is expressed in Eq 1.
where p0 and p1 are complex numbers that define the projections of on the basis states
and
.
Since complex amplitudes represent quantum states, quantum computation relies on the algebra of complex numbers. To establish the foundation, the representation of complex variables in both rectangular and polar forms, along with their arithmetic, is presented in Eqs 2–4 respectively.
These equations provide the mathematical foundation for describing quantum states, their transformations, and measurements.
Graphically, a qubit is represented on a unit sphere known as the Bloch sphere. In this model, the state of a qubit corresponds to a unit vector defined with respect to an orthonormal basis. The standard choice of basis is the computational basis, also known as the , denoted as
and
, placed at the north and south poles of the sphere, respectively. Any pure qubit state can then be expressed as a linear combination of these basis states and visualized as a point on the Bloch sphere, as shown in Fig 1.
The core concept of spin enables QC with superposition and entanglement. The following is the description of these properties.
- Superposition: states that a qubit can exist in a combination of basis states simultaneously, defined by complex probability amplitudes whose squared magnitudes give the measurement probabilities, unlike a classical bit, which deterministically represents either 0 or 1. The mathematical expression for superposition is defined as Eq 5.
(5)
(6)
The probability states, i.e.,is a complex number defined by a combination of real (
) and imaginary (
) parts. In Eq 6, P(.) denotes the probability of a measurement event.
The basis states () are represented as a column vector of dimension
, expressed in Dirac notation as a ket, as shown in Eq 7.
(7)
- Entanglement: It is a phenomenon where two or more qubits are linked, such that their quantum states cannot be described independently, even when separated by vast distances. Measuring the state of one entangled particle instantly determines the state of the other. Mathematically, the entangled qubits are represented as non-separable states in the tensor product space in Eq 8.
(8)
In the circuit model of quantum computation, wires carry logical qubits and quantum gates act on qubits, i.e., gates perform reversible phase shifts on the operand qubits. A quantum gate acting on n qubits has n wires as input and output, and a unitary matrix represents the gate. Figure 2 represents an n-qubit quantum circuit.
A quantum algorithm can be abstracted as a complex unitary operator acting on n qubits. In practice, this complex operator is broken down into a sequence of operations from a universal set of quantum gates, i.e., a set composed of 2-qubit entangling gates, such as CNOT, and all 1-qubit gates. Since provides arbitrary Z-axis rotation and Hadamard conjugates Z into X, the pair
generates arbitrary single qubit unitary operations via Euler angle decomposition. Together with CNOT, which is an entangling 2-qubit gate, the set
is universal for quantum computations [13].
Table 2 presents the rudimentary set of universal gates. CNOT gate takes n = 2 inputs, i.e., a control qubit and a target qubit
. The state of the target qubit alters based on the control qubit, resulting in entanglement.
2.2 Literature review on quantum emulations
The mathematics behind quantum information processing shows that a quantum algorithm can be represented as a series of unitary transformations, simplifying the quantum computing solution to matrix multiplications. The literature review indicates that emulation and simulation setups execute the state space representation of quantum circuits through matrix-based operations.
Over the past decade, FPGA-based quantum emulation has progressed from basic gate-level models to more sophisticated algorithmic abstractions. However, scalability and efficiency remain a persistent challenge. To improve gate accuracy, Giorgio et al. [14] proposed model-based design and optimized HDL, though fixed-point arithmetic still restricts scalability. Recent work by Conti et al. [15] and Lagostina et al. [16] focused on improving resource efficiency and, consequently, enhancing scalability. Despite these advances, hardware limitations continue to restrict both efficiency and scalability.
In addition to advances in FPGA-based quantum emulation, parallel research focuses on accelerating specific quantum algorithms, such as the Quantum Fourier Transform (QFT), Haar Transform, and Grover’s algorithm. Nedjah et al. [17] achieved speedups of 1.7 ns vs. 29.6 s for two qubits by using dedicated FPGA hardware, but support was limited to six qubits. Waidyasooriya et al. [18] implemented a 30-qubit QFT emulator, achieving 23.6x-24.5x speedup over CPU with high fidelity, but resource and synchronization challenges remained. El-Araby et al. [19] emulated up to 32 qubits with a 21.66x speedup for C2Q and a 3.49x speedup for QHT compared to CPU, along with a 25% reduction in circuit depth, though hardware demands quickly became prohibitive. Choi et al. [20] and Mahmud et al. [21] advanced Grover’s and QFT emulation, and achieved 6-qubit emulation on Kintex (vs. 4-qubit on Arty A7), with 191x performance boost over software. Still, approximation errors up to 6.25
10−4, scaling challenges with increasing qubit count, and exponential memory growth continued to limit large-scale implementations. In the comparative analysis, the architectures [16] and [21] indicate quantum emulation but do not explicitly specify the number of qubits. In such architectures, the number of representable qubits primarily depends on the register size and the allocation of available hardware resources.
Collectively, these works demonstrate the feasibility and potential of FPGA-based emulation. They highlight the need to improve hardware and design strategies to create an optimized, lightweight solution for scalable, general-purpose applications and to support larger, more complex quantum systems. Table 3 summarises the key hardware abstraction circuits presented in the literature, organised by gate-level and algorithmic-level approaches.
2.3 Baseline framework
Emulations are valuable for evaluating and developing quantum algorithms. These frameworks are inherently memory- and compute-bound, and scalability is ensured only by trading one for the other [12]. In 2021, Khalid et al. presented a Spartan-3-based abstraction of a noiseless single-qubit quantum system. The present work is an algorithm-level state-vector emulation that accelerates computation by preprocessing circuit matrices.
In the baseline framework, a qubit is represented in the form of probability states as per the expression given in Eq 5. Each probability state is represented as a pair of signed fixed-point numbers. Each probability amplitude is represented using signed (m + 2) bits fixed-point forma, i.e., Q(2,m), consisting of one sign bit, one integer bit, and m fractional bits. Although this format provides a dynamic range of [−2, 2–2-m], the effective range utilized in the proposed architecture is restricted to
, consistent with the normalization constraint of quantum states. Since probability amplitudes satisfy
, the additional integer range is not exercised during operation. The resolution of the representation is 2-m, i.e., the maximum quantization error per component. Increasing m therefore reduces amplitude quantization error and correspondingly decreases deviation from the ideal Bloch-sphere representation.
Collectively, a single qubit is given as Eq 9.
The FPGA memory representation of this matrix is a register file that stores four signed fixed-point numbers.
The setup demonstrates superposition and probabilistic measurement through single-qubit gates, i.e., Pauli-X, Pauli-Y, Pauli-Z, Hadamard, and measurement. An algorithmic simulation of Quantum Key Distribution (QKD) protocols, i.e., BB84 and B92, verifies the emulation framework by benchmarking the results against theoretical models [22]. Given the Q(2,6) fixed-point representation, the qubit emulation is termed as 8-bit state space representation in the base paper’s nomenclature. The baseline framework performs performance analysis on 8, 32, and 64-bit representations, and the results show that this FPGA-based architecture yields highly accurate results when a 64-bit state space represents the circuit.
Given the configurable nature of FPGAs relative to CPUs and GPUs, the control on accuracy achieved by emulation is promising. This highlights the need to extend the base framework by developing all gates in the universal set, including all single-qubit transformations and an entangling gate, such as the CNOT. Therefore, this paper is an extension of the base framework Artix-7 to include the following gates:
- Single-qubit gates, i.e., Phase, S and T gate.
- 2-qubit gate, i.e., CNOT transformation.
The subsequent sections present the extended architecture of the base framework, along with the associated experimental verifications.
3 System architecture of the extended FPGA emulator
The architecture of the proposed framework is designed to be hierarchical. The Finite State Machine (FSM) is the control module of the emulation that fetches the state vector of quantum information from the memory, transforms it using gates defined in the Arithmetic Logic Unit (ALU), and the result is then stored in quantum memory and can be exported to the measurement block for the classical output. The functional blocks, i.e., ALU, emulated memory, and measurement are composed of two subblocks: a single-qubit system and a 2-qubit system, to support a set of universal gates. Each quantum operation is defined as an instantiable module to ensure reusability and to reduce dependency among functional blocks. The block diagram of the system architecture is presented in Fig 3.
The proposed architecture adopts the same fixed-point representation model as the baseline framework without modification, ensuring direct comparability of numerical precision and performance. Each probability state is represented by two Q(2,6) signed numbers, i.e., to represent the real () and imaginary (
) parts of a complex state (C). The memory footprint of a single qubit is two probability states (
) as per Eq 5 stored as four Q(2,6) numbers in a register file. Similarly, 2-qubit representation requires four states, i.e.,
as defined in Eq 7 and represented by eight Q(2,6) registers stored in a register file.
In addition to this, the quantum operations are unitary, and qubit transformations through these gates are mathematically represented as matrix multiplication. Since the proposed emulation focuses on a lightweight architecture, the matrix multiplications are simplified to optimize the ALU’s computational resources. The details of quantum gate architectures and resource utilization summaries are presented in subsequent subsections. The implementation, including the Verilog source code, experimental workflow, and supporting files, is publicly available on GitHub [23,24].
For the cost-versus-accuracy analysis, the emulation architectures are scaled up to a 32-bit(Q(2,30)) representation. The detailed analysis of scaled-up emulation is presented in Section 5. The proposed quantum emulator is designed on Vivado Design Suite using Verilog, and the results are synthesized on Artix-7. The resource summary of the target board is given in Table 4.
3.1 Quantum memory block
In the standard Schrodinger’s approach, the superposition state vector represents an n-qubit system by -dimensional Hilbert space where
. In the baseline, i.e., n = 1 framework, a qubit, mathematically represented as Eq 5, is defined as a 21-dimensional complex Hilbert space and implemented as a register file consisting of four independent Q(2,6) signed registers. First two registers define
by storing
and
at address 002 and 012 respectively. C1 is stored similarly in the subsequent registers. The Q(2,6) signed fixed-point register file enables the quantum memory to accurately represent the computational basis at the cost of over-provisioning for qubit representation.
This work proposes a n = 2 quantum information representation through 22-dimensional complex Hilbert space. The mathematical description of the state vectors is given in Eq 10.
To represent four complex numbers of the form , a register file of structure
is used to represent a 2-qubit system.
Figure 4 presents the memory architecture to store n-qubits, where . The write flag enables the
Decoder and
Mux for read and write operations at binary values 1 and 0 respectively. The register file acts as an n-qubit flip-flop, i.e., the complete file is read sequentially to access the state vectors of quantum information.
3.2 Measurement block
The base paper’s measurement architectures employ multi-shot sampling to convert quantum information into classical bits. This process refers to repeated probabilistic measurements of an identically prepared quantum state over N trials, in which empirical outcome frequencies approximate the theoretical probabilities.
In a single measurement instance, a Permutation-based Shuffling (PbS) function generates a fixed-point pseudo-random number (PRNG) in the interval [0, 1]. If the PRNG lies within the interval [0, ], the outcome is recorded as
; otherwise the qubit is measured as
[12]. This procedure emulates the stochastic nature of quantum measurement, in which the squared magnitudes of the probability amplitudes determine the likelihood of each outcome.
The proposed upgrade of this block involves the inclusion of a two-qubit measurement to facilitate the calculation of the classical output of the CNOT gate. The architecture is based on a probabilistic sampling principle.
The general state of a 2-qubit system is represented as Eq 14 with the normalised condition on amplitudes.
For measurement, the interval [0,1] is divided into four subintervals according to the probability distribution of basis states, as elaborated in Eq 15.
Each subinterval corresponds to the states ,
,
,
respectively. For each measurement instance, PbS function generates a PRNG. The measurement outcome is then determined as the basis state whose probability interval contains PRNG. Figure 5 is the abstract level representation of 2-qubit measurement emulation.
In the proposed architecture, each measurement experiment defined in section 5 is executed over 100 shots to implement multi-shot sampling. The resulting empirical frequency distribution converges to the theoretical probabilities defined by the Born rule. The selection of 100 shots provides a balance between statistical reliability and computational efficiency. Furthermore, this configuration ensures methodological consistency with the IBM quantum platform, which similarly reports measurement outcomes using repeated-shot sampling.
3.3 Arithmetic logic unit
The ALU is the computational module of the emulation framework that performs quantum state transformation through a sequence of gates scheduled by the FSM and defined by a quantum circuit, i.e., a standard mathematical model to describe computations. Figure 2 presents a generalised quantum circuit that transforms n-qubits through a unitary gate.
This unitary gate can be further simplified to a sequence of unitary gates, i.e., a finite set of elementary gates capable of constructing non-trivial quantum computations. Formally, a set of gates is said to be universal if it is composed of all single-qubit gates and a 2-qubit entangling gate [13]. The base framework partially emulates the universal set, i.e., Pauli-X, Pauli-Y, Pauli-Z, and Hadamard gates. Whereas the proposed work incorporates the remaining single-qubit gates and an entangling 2-qubit gate, completing the set defined in Table 2. The emulation architectures of the designed gates are as follows:
3.3.1 Single-qubit phase gate emulation.
Single-qubit transformation reflects the rotation of the corresponding state vector on the Bloch sphere. Discrete unitary operators are Pauli gates, as these gates apply a rotation over the reference axis. On the other hand, Phase gates use finer control over azimuthal rotation on the Bloch sphere, i.e., a continuous rotation of the state vector by angle
along the z-axis.
The mathematical representation of the Phase gate () transformation is given in Eq 16 and 17. This transformation leaves the
state unchanged, and applies a phase (
) to the
. The matrix multiplication used to perform a qubit rotation is algebraically simplified as Eq 19 to reduce computational overhead. The micro architecture of the Phase gate as per the expression given in Eq 19 is presented in Fig 6. This architecture takes the input probability state and the phase value in radians. The output of this block is the transformed qubit, i.e.,
.
For demonstration purposes, the input is initialised as and
. The trigonometric expressions are represented as signed Q(2,6) numbers. The discretization of these expressions due to fixed-point representation affects the accuracy of the emulation output compared to the theoretical results. Figure 7 presents a comparison between the emulation results and the theoretical predictions in terms of quantum state probabilities for the test inputs, i.e.,
and
. The Artix-7 based resource utilization summary of Phase gate emulation is given in Table 5.
S and T gates are special-purpose phase gates that shift the qubits’ azimuthal angle by and
radians, respectively, keeping the probability amplitude intact. Given the applications of these gates in error correction and fault-tolerant quantum computing, separate emulation modules are designed for these operations. The following are the microarchitectures, resource utilization summaries, and theoretical benchmarking of these special-purpose gates.
1. S-Gate: The gate rotates the state vector by radians about the z-axis. The application set of the S-Gate includes phase correction, Quantum Fourier Transform, and stabilizer circuits.
The linear operator representation in Hilbert space is given in Eq 20. Whereas, the algebraically simplified form of this unitary gate is presented in Eq 22 and is implemented using the microarchitecture given in Fig 8. The resource utilization summary and output comparison with the theoretical model for input are presented as Table 6 and Fig 7 respectively.
2. T-Gate: This gate is responsible for the phase shift of the input qubit about the z-axis. The T-Gate is the functional building block of the universal gate set. Eq 23 presents the gate’s unitary matrix. Whereas, the algebraically simplified form of this unitary gate is presented in Eq 25 and is implemented using micro architecture given in Fig 9. The resource utilization summary and output comparison with theoretical model for input
is presented as Table 7 and Fig 7 respectively.
The emulation architecture of the Phase, S, and T gates represents the algebraic simplification of complex matrix multiplications involved in applying unitary operators.
3.3.2 Two qubit gate emulation.
The CNOT gate is a fundamental 2-qubit operation that enables entanglement generation, completes the universal gate set, and acts as an analogue to the classical Xor gate in the quantum domain. In the CNOT gate, the control qubit governs the transition of the target qubit. Mathematically, it is represented as a matrix multiplied by the tensor product of input qubits, i.e., control and target qubits, as shown in Eq 27. A separate module for the tensor product is designed to serve as a prerequisite for the CNOT gate. The architecture is based on the algebraic simplification in complex arithmetic as defined in Eq 3 and 4.
To ensure accuracy and resource efficiency, the behavioural architecture of the gate is emulated as shown in Fig 10, and the corresponding resource utilization metrics are summarized in Table 8. The results of the gate with inputs are elaborated in Fig 11.
A common implementation insight in all the above proposed architectures is that the Block RAM (BRAM) was not employed. The reason for this design choice is that the small state space of the targeted quantum systems favors register-based storage, enabling single-cycle access and efficient amplitude permutation without incurring BRAM access overhead.
3.4 Finite state machine
The FSM is a control module that invokes the memory, ALU, and measurement blocks based on the user-defined quantum circuit. In line with the sequential computational model of the quantum circuit, for a given quantum system, the FSM serially instantiates the quantum gates for input transformations, stores the resultant state in quantum memory or directs the measurement block to produce the classical output.
Figure 12 presents a generalised FSM for a single gate emulation. The FSM starts on the positive edge labeled Start. The input qubits are transitioned according to the selected gate (Phase, S, T, CNOT). The output is then stored in the register file, and the process concludes at the Finish stage.
Figure 3 defines an independent setup capable of executing quantum circuits since it can emulate the universal gate set. To validate the claim, a computational procedure for the emulation of an arbitrary unitary single gate is presented in the subsequent section.
3.5 Arbitrary single-qubit gate emulation
The universality in single-qubit transformation requires two single-qubit gates (rotation) as defined in Eq 29.
where l and m are non-parallel axes of the Bloch sphere and [13]. In classical mechanics, the Euler Rotation Theorem states that any orientation of a 3D unit vector on a sphere can be achieved by three rotations, i.e.,
, about two orthogonal (non-parallel) axes. Relating the Euler rotation theorem to the condition for a universal set, any arbitrary state transformation of a qubit on the Bloch sphere can be accomplished by rotations about two non-parallel axes, i.e., rotation along the z and x axes.
Therefore, by virtue of the Euler rotation theorem, the expression of single qubit transformation universality is given in Eq 30.
The above expression can then be simplified as standard quantum operations, i.e., Phase and Hadamard gates, as given in Eq 31.
Where and
refer to rotation along the z-axis, and
is rotation around the x-axis. This Z-X-Z decomposition is used in industry-standard frameworks like Qiskit, and is adopted in the proposed emulator. For the emulation of a single-qubit unitary gate, i.e.,
, Phase and Hadamard gates will be instantiated in the following order.
: Adjusts the relative phase of the input state.
: Changes the latitude of the qubit
: Adjusts the longitude of the qubit
Figure 13 presents the FSM for the arbitrary single qubit transformation. For experimental verification Fig 14 the results of applying a single-qubit arbitrary transformation to the input state , using the universal parameter set
with angles
,
, and
respectively.
The subsequent section presents the validation of the proposed architecture by implementing rudimentary quantum circuits.
4 Implementation of quantum algorithms
To verify the correctness of the proposed emulation framework, five foundational circuits from quantum computing are executed, i.e., Bell state preparation, Deutsch’s algorithm, Superdense coding, Grover’s search, and BB84 Quantum Key Distribution (QKD). The premise behind choosing these use cases is to confirm superposition handling, represent entanglement within the computational architecture, and assess functional accuracy. The implementation details of these quantum circuits are as follows:
4.1 Bell states generation
Bell state generation is a 2-qubit circuit that first creates a superposition by applying a Hadamard gate on the first qubit, followed by a CNOT gate to entangle it with the second qubit, producing states as shown in Fig 15. The resulting entangled pairs serve as fundamental resources for protocols such as quantum teleportation and superdense coding. The successful emulation of Bell circuits verifies the capability of the proposed architecture to realize entanglement, one of the essential requirements for a universal gate set.
Figure 16 depicts the control-driven execution flow diagram that incorporates four Bell states (,
,
, and
). The output of any selected Bell state is first stored in the quantum memory and subsequently directed to the measurement module for classical data generation. The coordinated control logic guarantees precise timing and accurate emulation throughout all operational stages. The emulation results for the Bell states closely align with theoretical benchmarking, as shown in Figs 17–20.
4.2 Deutsch algorithm
Deutsch’s algorithm is a two-qubit rudimentary circuit that determines whether a Boolean function y = f(x) is constant or balanced in a time-efficient manner. The algorithm flow includes the translation of the classical function (f(x)) into an oracle that is then embedded in Deutsch’s circuit.
For the validation purposes, the phase oracle of the Xnor gate is tested on the Deutsch algorithm as presented in a quantum circuit and control-driven execution flow diagram as given in Fig 21 and 22 respectively. Since Xnor is a balanced function, the expected measurement result of the least significant qubit should be 1. The results for the emulation circuit in comparison with the theoretical results are presented in Fig 23.
4.3 Superdense coding circuit
Superdense coding enables communication of two classical bits, i.e., (c,d), through a single-qubit over a quantum channel between Alice (Sender) and Bob (Receiver) at the expense of one entangled bit, i.e., . By applying conditional Pauli operations
to her half of the entangled pair, Alice encodes four distinct orthogonal states, which Bob subsequently decodes through a Bell-basis measurement (CNOT followed by a Hadamard gate).
Figure 24 illustrates the circuit for communication of (c = 1,d = 1) from the sender to the receiver. In the given circuit, the Bell state is prepared at barrier 2, followed by the application of
. Barrier 4 depicts the communication channel, and Bell state measurement is performed at the receiver end on barrier 6.
Since an emulated quantum communication channel is beyond the scope of the proposed work, both the sender’s and receiver’s sides are defined in a unified FSM, where conditional Pauli operations on q0 result in classical information (c,d) translation onto the measurement results of qubits q1 and q0 respectively. The controller-driven execution flow of superdense coding for transmitting (c,d)=(1,1) with both qubits initialized to is shown in Fig 25.
According to the circuit analysis, the measurement results should predominantly give the classical output of 11. Fig 26 presents the output of emulated superdense coding that is aligned with the theoretical outcome.
The proposed two-qubit emulation module is designed as a reusable building block that can be instantiated multiple times to support the parallel execution of independent quantum circuits. This scalability is demonstrated in section 5 through the parallel implementation of eight independent two-qubit Superdense Coding circuits for the communication of a 16 -bit binary word, rather than through the emulation of a single 16 -qubit quantum state.
4.4 Grover’s search algorithm
Grover’s Search (GS) algorithm is an unstructured search algorithm that gives the output in iterations, in contrast to the N iterations required by classical systems. The algorithm comprises two parts, i.e., the Phase-Oracle, which flips the phase of the marked state, and the-diffuser, which amplifies the marked state. Figure 27 presents the circuit for 2-qubit GS. This circuit gives the marked state, i.e., 01, in
iteration instead of 4 = 22 iterations when the oracle is searched classically. Figure 28 presents the execution flow for the given circuit, while Fig 29 represents the measurement results of the emulated circuit (using top down approach), benchmarked against the theoretical output obtained through sequential mathematical analysis of the circuit. In this flow diagram, the transformation of the H-CNOT-H gate, i.e., the application of the controlled-Z gate, is emulated within the at thFSMe behavioral level to ensure a cost-effective implementation.
4.5 The BB84 quantum key distribution
BB84 is a communication protocol that provides information theoretically secure key distribution over a quantum channel using a pair of orthogonal bases. For emulation, the selected base pair is Z and Y. Using bases and keys randomly generated at the sender’s end, the protocol emulation achieves a key-agreement rate of 76.75% at the receiver’s end. Table 9 shows the working of QKD for the distribution of key = 01001010.
Since BB84 is a communication protocol, instead of a control flow diagram, the architectures of the sender and receiver modules are designed. Figure 30 presents the sender module, where the key and bases are randomly selected, and, based on the selection, the classical key is transformed into quantum information, bit by bit.
At the receiver’s side in Fig 31, the received quantum information is processed qubit by qubit. Each qubit is measured against randomly selected bases, i.e., Z or Y, to generate a classical key. Since the proposed emulation is designed for the Z basis, the application of the Phase gate followed by the Hadamard gate replicated the effect of measurement in the Y basis.
The experiment runs across 100 instances, and Fig 32 shows that the average key agreement rate in the emulated setup is 76.75%, i.e., comparable with the theoretical rate of 75%.
5 Performance analysis
The emulator stands out as a highly reliable tool for evaluating the performance of quantum algorithms, ensuring that experimental probabilities align closely with theoretical expectations. The architecture presented in Section 3 uses a Q(2,6) fixed-point representation for quantum emulation. This quantizes the Bloch sphere and introduces truncation error. Thus, to improve emulation performance relative to the theoretical results, the register size may be extended to a Q(2,30) fixed-point representation. This would improve the precision of algebraic calculations, making the system accurate. Table 10 presents a synthesis report on the primary gate’s accuracy and resource utilization on the Artix-7, illustrating the inverse relationship between accuracy and implementation cost. Specifically, for unitary gates(S, T and Phase), the Table 10 shows that the emulator effectively reproduces the expected magnitudes of |C0| and |C1| for the and
states, respectively, with the input
and phase angle
used in phase gate. For a 2-qubit system, the result of CNOT with inputs
and
is as shown in the Table 10. The deviation from the theoretical outcomes is minimal, as indicated by the error rates.
The primary contributors to the emulation error are as follows:
- Qubit error: At the input, when a qubit is stored within a register file utilizing a six-bit precision, the superposition states of the basis are subjected to quantization, resulting in an inherent representational error for the qubit. Additionally, the fixed-point representation of qubit flip-flops results in truncation of gate outputs, thereby introducing computational inaccuracies.
- Quantum unitary gate error:The fixed-point (Q(2,6)) gate representation introduces an error due to the presence of irrational numbers within the matrices of unitary gates, including the Phase, S, T, and CNOT gates, which are integral to the quantum circuit design.
- Multiplication error: Multiplication errors occur during gate operations on the FPGA emulator due to rounding and truncation in fixed-point calculations. These errors propagate through subsequent operations, significantly reducing qubit state fidelity.
- Measurement error: Measurement errors in quantum systems can occur because the Pseudo-Random Number Generator (PRNG) used for qubit state measurements produces values with limited precision. Since the PbS function generates eight-bit integer outputs, the discrete nature of the PRNG reduces the accuracy of qubit measurements, leading to quantization errors that impact the precision of the results.
The errors illustrated above demonstrate an inverse relation with register size, as elaborated in the Table 10. The error is quantified as the difference between the emulator outcomes and the corresponding theoretical results, as shown in Eq 33. To rigorously quantify the discrepancy between the theoretically predicted and emulator-obtained amplitudes of a single-qubit state, the error was first assessed by calculating the magnitudes of the resulting coefficients. The magnitude of the emulator amplitude is defined as:
The absolute amplitude deviations are then computed as
Finally, the relative percentage errors are calculated according to
Error rate decreases from 3.1% at Q(2,6) to 2.15% at Q(2,30) for the CNOT gate. This improvement in accuracy is associated with higher resource utilization. Look Up Tables (LUTs) and slice counts rise from 1921 to 2791 and 748 to 879, respectively. This reflects a trade-off between precision and computational resources.
Furthermore, the performance of the base operators in the proposed work is benchmarked against a commercial simulator and IBM Quantum Hardware. The comparison circuit comprises qubit initialization, a unitary transformation, and a 100-shot measurement. Table 11 shows that the proposed FPGA emulator achieves significantly lower execution time, primarily due to the inherent parallelism and fine-grained logic control offered by FPGA technology. It should be noted, however, that the FPGA emulator, IBM Aer simulator, and IBM Quantum Hardware represent fundamentally different execution environments. Consequently, the comparison is intended for functional benchmarking rather than a direct hardware-performance evaluation.
The reduction in measurement accuracy observed for the proposed emulator under the given experimental setup is primarily attributable to the limited shot count and the pseudo-random nature of the measurement module, whereas the deviations observed on IBM Quantum Hardware arise from physical noise sources such as gate errors, decoherence, and readout errors. This observation is further supported by the high accuracy of the quantum state representation during unitary transformations, as presented in Table 10.
Table 11 also includes the energy consumption of the proposed FPGA emulator and the IBM Aer simulator to provide additional perspective on the resource-efficient nature of the proposed FPGA implementation. The synthesized gate’s dynamic power was estimated in Vivado and converted to energy per operation, ranging from 3.34375 nJ to 23.31429 nJ for the evaluated gates. For IBM Aer, energy was calculated as the CPU package power measured using Intel Power Gadget multiplied by the execution time (). The FPGA values represent gate-level logic power, whereas the IBM Aer measurements include whole-system CPU overhead, such as operating system and memory activity. Owing to the heterogeneous architectures and fundamentally different measurement methodologies, the two results are not directly comparable. Consequently, the reported energy values are intended only to provide qualitative insight into the resource requirements of the proposed FPGA implementation, rather than to support absolute energy-efficiency comparisons. For IBM Quantum Hardware, per-gate energy is reported as unavailable due to cloud-managed hardware access, since users cannot access the hardware-level power or energy measurements required to estimate individual gate energy.
From the perspective of a quantum circuit, the parameters used to quantify the magnitude of computations are:
- Width (W): The total number of qubits utilized.
- Depth (D): The number of sequential gate layers applied.
The discussion on scalability and error accumulation in a quantum circuit when executed on the emulator is as follows:
1. Width Analysis: From an 8-bit emulation viewpoint, each additional qubit introduces extra state-storage overhead. In the proposed implementation, the quantum state associated with one qubit is represented using a register file storing four Q(2,6) signed values (32-bits). The current prototype demonstrates accurate emulation of a small quantum instance with width W = 2 and depth D = 6, i.e., the Deutsch algorithm, validating correct fixed-point gate sequencing and 2-qubit entanglement generation. At this scale, the required state storage remains manageable, since only a limited number of correlated amplitudes must be maintained.
However, as circuit width increases and multi-qubit entanglement becomes more complex, the underlying quantum state can no longer be described with such limited storage. In general, highly entangled systems require tracking complex amplitudes, implying that memory and datapath requirements scale exponentially as
with the number of qubits.
Thus, while small-width emulation can be achieved efficiently, scalability beyond a few qubits is fundamentally constrained by the exponential growth of the state space, which represents a primary performance limit for quantum circuit simulators and emulators.
Long-term scalability may be pursued through architectural extensions such as BRAM-based state storage, distributed multi-FPGA partitioning, hybrid FPGA – GPU acceleration, or approximate simulation techniques (e.g., tensor-network or algorithm-specific reduced-state methods). These directions provide a pathway toward supporting larger post-quantum cryptanalytic workloads in future work.
2. Depth Analysis: In the emulation architecture, a single increment in the depth refers to the instantiation of a quantum gate emulation circuit, followed by storing the output in a quantum memory block. In this process, the following errors affect the accuracy of the output state probabilities.
- The input is quantized in the form of Q(2,6) fixed-point representation of probability states. This limits the superposition states of a qubit.
- Since the unitary operators are expressed as matrices, and every entry of these matrices is expressed in Q(2,6) signed fixed-point number, an error is introduced in gate representation.
- Qubit transformations are implemented using matrix multiplication, which involves multiplication followed by addition in fixed-point representation. In a Q(2,6) system, multiplying two fixed-point values expands the intermediate result to Q(5,12) due to bit growth in both integer and fractional parts. According to the emulation architecture, this Q(5,12) result is then truncated back to Q(2,6) to maintain the defined fixed-point format as per the emulation architecture.
For demonstration purposes, a phase gate is applied to the state to achieve a complete
rotation on the Bloch sphere, i.e., sequential applications of
for eight consecutive iterations. Table 12 presents the gate depth analysis of the proposed emulator.
The depth analysis indicates that truncation-induced error accumulates approximately linearly with circuit depth in the Q(2,6) fixed-point representation. After eight consecutive phase operations, the observed amplitude deviation reaches approximately 0.125, which closely corresponds to . The term 2-6 arises from the fractional precision of the Q(2,6) format, where six bits are allocated to the fractional part, yielding a resolution of 2-6 = 0.015625.
This behaviour confirms that the dominant source of inaccuracy originates from repeated fixed-point truncation, leading to cumulative error proportional to the number of gate applications. Consequently, while the Q(2,6) representation is suitable for shallow circuits, deeper quantum circuits benefit from higher-precision formats such as Q(2,30) to mitigate error growth.
The Bell-states creation and the Deutsch algorithm with f(x) are executed on all three setups. Table 13 presents the performance of these setups compared to the theoretical ground truth. The IBM QC () platform exhibits noise, instability, and error rates of
for 2Q (best),
for 2Q (layered),
for CZ, and
for SX. These errors stem from decoherence and noise, directly impacting its performance [25].
Similarly, the Superdense coding and Grover Search algorithms were executed and evaluated across all three setups. The IBM QC platform (ibm_fez) exhibits noise, instability, and error rates of for 2Q (best),
for 2Q (layered),
for CZ, and
for SX, which adversely affect its performance during quantum computations [26]. The proposed emulator is independent of environmental noise and cannot, thus, be compared one-to-one with the actual quantum computer. The IBM simulator, on the other hand, uses a state-space representation of qubits; thus, it can serve as a valid benchmark for the proposed work.
Table 13 shows that the Q(2,6) emulation architecture produces results comparable to those of the open-source IBM simulator. Therefore, the proposed Q(2,6) emulation architecture is a standalone framework that can execute quantum circuits and produce results comparable to those of a globally recognized open-source simulator, i.e., the IBM-Aer simulator. Table 13 provides a comprehensive overview of the accuracy and resource utilization of quantum computing algorithms. It underscores the emulator’s proficiency in replicating the expected probabilities of Bell-States, with square magnitudes ,
,
, and
, using inputs
and
for both qubits. The deviation from theoretical results remains minimal, with the emulator’s average error rate at 2%, compared to 2.25% for the IBM simulator and 3.5% for IBM-QC. This precision extends to the Deutsch algorithm with the Xnor function, where the emulator achieves an error rate of 14%, compared to 16% for IBM-Aer and 22% for IBM-QC.
The Superdense Coding protocol was scaled by executing eight independent 2-qubit circuits in parallel, enabling the transmission of a 16-bit binary word (0x781B). The IBM-Aer simulator provides ideal, noise-free state-vector simulation and therefore achieves near-perfect accuracy. The proposed FPGA emulator exhibits a small reduction in accuracy due to finite precision arithmetic and measurement sampling effects. In contrast, IBM quantum hardware is subject to physical noise sources, including gate errors, decoherence, and readout errors, which contribute to greater deviations from the theoretical result, particularly when a limited number of measurement shots are used, as reported in Table 13. The resource utilization results indicate that sufficient LUT resources remain available on the Artix-7 FPGA, suggesting the potential to further scale the same Superdense coding implementation to support larger message widths.
The Grover Search algorithm was implemented as a 2-qubit circuit targeting the marked state . The IBM-Aer simulator achieved the ideal noise-free result with a 0% error rate. The proposed FPGA emulator exhibited an error rate of 7%, primarily due to finite-precision arithmetic and measurement sampling effects, while utilizing 3977 LUTs and 3410 slices, as reported in Table 13. In contrast, the IBM quantum hardware produced an error rate of 9%, which can be attributed to physical noise sources such as gate errors, decoherence, and readout errors. Consequently, the FPGA emulator demonstrates performance that is closer to the theoretical ground truth while providing a resource-efficient platform for quantum algorithm emulation.
Two key features that determine the completeness and fidelity of a quantum emulation architecture are the inclusion of a measurement module and validation against a standard reference simulator. Architectures that incorporate both features can be regarded as complete in functionality and reliable in accuracy.
Table 14 presents a comparative analysis of the proposed system with the emulator available in the literature based on the metrics, i.e., the size and complexity of the quantum circuits used for functional verification, the target FPGA platform, hardware resource utilization, and the numerical precision employed for the classical representation of quantum states.
The target boards for emulations [27,28] and [14] are DSP-enabled and are equipped with high on-chip memory. This gives the proposed design the ability to emulate large quantum circuits at the cost of the hardware. In contrast to that, the proposed emulator and the architectures defined in [16] and [15] are executed on resource-constrained boards with limited memory.
Despite the limited hardware resources, the proposed emulator incorporates a measurement module along with a pseudo-random number generator (PRNG) and demonstrates functional verification across a diverse set of quantum algorithms, including the parallel execution of eight independent 2-qubit Superdense Coding circuits defined in Section 4.3 for the communication of a 16-bit binary word and a Grover’s Search with the circuit depth of 11. Furthermore, the resource utilization analysis indicates that sufficient FPGA resources remain available after implementing the parallel Superdense Coding modules, suggesting that additional independent 2-qubit modules can be instantiated on the target Artix-7 platform. These results demonstrate the scalability of the proposed architecture through modular replication of the underlying 2-qubit emulation framework.
This enhanced performance is attributable to the emulator’s efficient gate transformations. The process entails transforming input qubits with specified gates, followed by measurement and storage in qubit memory. A base-function cost analysis reinforces the emulator’s resource-efficient performance. Table 15 presents a comparative analysis of the proposed work with the baseline framework in order to quantify the proposed improvements.
The analysis shows that the proposed solution offers a universal set for quantum computation on Artix-7, in contrast to superposition emulation on the relatively older board, i.e., Spartan-3, used in the baseline framework. This universality enables the emulation of a greater set of quantum circuits in a resource-efficient manner. In addition, the performance evaluation metrics, including gate-depth sensitivity analysis and functional benchmarking against the IBM platform, provide quantitative evidence of the accuracy, robustness, and practical reliability of the proposed FPGA-based quantum emulation framework.
6 Conclusions
In conclusion, the proposal for an FPGA-based emulator implemented on the Artix-7 board using a behavioral model approach offers a cost-effective, scalable platform. It efficiently simulates quantum unitary gates, yielding results comparable to theoretical outcomes. The proposed architecture is designed for Q(2,6) and Q(2,30) fixed-point data representation, demonstrating the tradeoff between computational resources and the emulator’s efficiency. To validate its performance, Bell states, Deutsch algorithm (for balanced function), Superdense coding, Grover’s search, and BB84 QKD were successfully emulated on a Q(2,6) architecture, yielding average error rates of 2%, 14%, 4%, and 7% respectively. The results demonstrate that the proposed emulator provides functionality comparable to that of the IBM-Aer simulator while offering improved resource efficiency, scalability, and hardware realizability. These characteristics make it a practical framework for verifying and testing quantum algorithms on FPGA platforms.
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