https://orcid.org/0000-0002-1001-4858
Figures
Abstract
This paper proposes a new grid-tied transformer-less boost switched capacitor topology (TLBSCT) that employs three capacitors and twelve switches to generate seven levels with a gain of three times. The salient features of the TLBSCT are its boosting capacity, zero leakage current, minimum switching devices and lower voltage stress. The capacitors of the proposed TLBSCT have self-balancing characteristics. The proposed TLBSCT offers a brief discussion of the configuration, principle of working and the design of the parameter, as well as its control scheme. In addition, a comparative study of the proposal against the current transformerless inverter (TLI) shows the better performance of the proposed approach(PA). Also, the theoretical concept and viability of the suggested design have been demonstrated by simulations and experiments. This work contributes to SDG 7: Affordable and Clean Energy by improving efficient and reliable grid-connected solar power conversion systems.
Citation: Samantara S, Krishna AM, Jena K, Gupta KK, Kumar D, Dewangan NK (2026) Grid-tied Transformer-less Boost Switched Capacitor Topology (TLBSCT) for PV applications. PLoS One 21(7): e0352760. https://doi.org/10.1371/journal.pone.0352760
Editor: Dhanamjayulu C, Vellore Institute of Technology, INDIA
Received: January 6, 2026; Accepted: June 15, 2026; Published: July 6, 2026
Copyright: © 2026 Samantara et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Data Availability: The data that support the findings of this study are available within the manuscript.
Funding: The author(s) received no specific funding for this work.
Competing interests: The authors have declared that no competing interests exist.
1. Introduction
The rising demand for renewable energy sources (RES) is driven by critical global challenges such as air pollution, climate change, and the finite availability of fossil fuels. Consequently, there is a steady global increase in the integration of RES, especially photovoltaic (PV) systems, into power grids. Power converters play a crucial role in interfacing PV systems with the electrical grid. Various configurations are employed for grid integration, primarily categorized as transformer-based inverters (TBIs) and transformerless inverters (TLIs).
In order to improve operational safety and system protection, transformer-based inverter TBI designs offer galvanic isolation between the source and load. But adding transformers decreases efficiency and power density, and it also enhances the overall cost, volume and weight of the system. A lot of people have been looking at TLI topologies as a solution to these problems recently. The advantages of TLIs over conventional TBI systems for residential solar applications include a smaller footprint, cheaper production costs, a lighter structure, less leakage current, and higher conversion efficiency [1,2]. For PV installations that are connected to the grid, a new topology for single-phase TLIs is presented in [3]. The proposed design aims to reduce leakage current by maintaining a constant common-mode voltage (CMV) and addressing issues with traditional TLIs.
TLIs offer several advantages; nevertheless, the primary negative aspect is the absence of galvanic separation between the PV array and the utility grid. This direct electrical connection causes leakage currents to flow from the PV array to the ground, which may cause additional power losses, grid current distortion, electromagnetic interference, deteriorated system efficiency and potentially safety hazards [4–6]. Several MLIs have been proposed in the literature to tackle the above problems. [7] proposes a five-level SC based neutral-point clamped (NPC) inverter by adding a SC unit to the conventional three-level NPC configuration. The architecture can provide a 5-level output voltage. The output voltage magnitude is limited to half the input voltage, giving a voltage gain of only 0.5. [8] shows the 5L-SC-ANPC and this architecture demands a high number of power switches and the related gate driver circuits, which increases the total control complexity. A hybrid inverter structure based on T-type topology and cascaded SC cells is proposed in [9]. This topology connects the neutral point of the AC output with the middle of the DC bus, thereby reducing the common-mode voltage. However, the configuration still uses a lot of components and suffers from high voltage stress in the semiconductor devices. In addition, the five-level SC based ANPC design proposed in [10] provides unity voltage gain with six switches, two diodes and three capacitors. However, the demand for higher DC-link voltage and higher RMS current leads to higher conduction losses and hence lower system efficiency.
In the ANPC design, the leakage current can be greatly reduced by connecting the grid neutral line with the middle of the DC bus [10–13]. There are a few drawbacks to this method, though. For one, the DC-link voltage must be twice the peak grid voltage. Secondly, there must be more switching components. Lastly, the leakage current problems are not entirely fixed. As a typical topology design for effectively mitigating leakage current [14–17] introduces the idea of a Virtual DC bus. By utilising a virtual DC rail, this connection permits the generation of negative voltage. Still, the complexity and cost of the aforementioned topologies skyrocket since they call for more active and passive switching components. Reference [18] proposes a seven-level switched-capacitor boost inverter, which links an output converter and a DC-link converter through a bidirectional switch to achieve seven voltage levels with a gain of just 1.5. The maximum voltage delivered to all power switches is not higher than the input DC voltage. The seven-level MLI presented in [19] produces a voltage gain of just 1.5 with nine switches and three capacitors. In reference [20], the ANPC inverter topology with seven levels, eight switches, two diodes and four capacitors is recommended. The architecture may generate multi-voltage levels, but an additional capacitor voltage balancing circuit based on closed-loop control is required to enhance the multi- voltage levels, which will raise the complexity and implementation difficulty of the whole system. The MLIs in [21] and [22] are using ten switches, two diodes and three capacitors, but the voltage gain is just 1.5. Moreover, these arrangements have a high total standing voltage per unit (TSVpu), requiring the semiconductor devices to have higher voltage ratings. According to [23,24], 7-level SC topologies include more switching components and TSV. The topologies of high-gain SCs are covered in [25,26]; the MBV of these topologies is equal to the load voltage. SC topologies with a low device count are addressed in [27,28]. However, in these topologies, the MBV is exactly the same as the load voltage. Additionally, the control techniques in [29–31] employ fuzzy logic control for enhanced energy extraction and minimized mechanical stress on the system with ultra-capacitor-based energy storage to compensate for abrupt power fluctuations and to ensure power balance during transient operating conditions. Conventional common-ground voltage-boosting topologies reported in [32–34] effectively reduce leakage current. However, these configurations require a larger number of components, resulting in increased circuit complexity and cost.
Drawing from the discussion in the preceding sections, this work introduces a TLBSCT that offers several notable advantages:
- The PT provides a voltage gain of 3 times while utilising 12 switches.
- The capacitors possess inherent self-balancing properties, eliminating the need for additional circuits or sensors to maintain voltage balance.
- It uses a reduced number of switching components.
- The switches are subjected to stresses with low voltages.
- The PT has zero leakage current
- Lower MBV
- It is suitable for low-voltage applications
- It can operate for different load power factors
The TLI structural details, working mechanism, and control strategy are thoroughly explained. The losses associated with the SC topology are also analyzed. The proposed TLI is compared with other existing designs, with a focus on its superior performance. Experimental results for both grid-connected and standalone modes are included to confirm the practicality and effectiveness of the proposed TLI.
2. Proposed topology
- (a) Description of the circuit diagram
The conceptual circuit of the proposed 7-level boost SCMLI is represented in Fig 1. The PT used twelve switches, three capacitors, and a single DC supply (of voltage) through which the output voltage can yield seven different values that include levels
, and
, resulting in a three times voltage gain, thus the input voltage can be attained from a lower DC voltage, such as that supplied by a PV panel. The DC supply charges the capacitors fully and there are no additional sensors needed to maintain the source voltage (
) across SC in this topology, thereby reducing cost. Moreover, this topology is configured so that all power devices have lower blocking voltages as well and there is a three-voltage-boosting factor. It can push low DC voltage from PV panels, fuel cells, or electric vehicle battery storage banks up to quality AC output voltage. Table 1 illustrates the switching logic of the PT.
- (b) Working Principle
The working principle of the PT is explained through seven separate operating modes
Mode .
In Mode , the output voltage is zero, as indicated by the conduction path for the load current (represented in red). The switches S2, S3, S5, S8, S10-, and S12 are in the ON state. Moreover, the capacitors C1, and C2 are both charged to
, because they are both connected in parallel with the input DC source, as seen in the blue conduction line. The circuit representation corresponding to this mode is shown in Fig 2.
Mode .
Switches S2, S3, S5, S6, S9, and S11 are turned on, enabling the load current to follow the red-marked path, while the capacitor current flows along the blue-marked route. The output voltage is , with both capacitors, C1 and C2, connected across the input
to maintain self-voltage balance. The circuit representation corresponding to this mode is illustrated in Fig 3.
Mode .
Mode is depicted in Fig 4. Switches S2, S4, S6, S9, and S11 are activated, allowing the load current to follow the red-marked path, while the capacitors’ current flows along the red-marked route. Capacitor C2 discharges through the load, increasing the output voltage to
without the need for any additional switch. Meanwhile, capacitor C1 remains connected in parallel with the input DC supply through S2, ensuring it charges to a voltage of
. C3 remains connected in parallel with the input DC supply and capacitor C2 through S8 and S10, ensuring it charges to a voltage of
.
Mode .
Mode is depicted in Fig 5. Switches S3, S4, S6, S7, S10, and S11 are turned on, enabling the load current to follow the red-marked path, while the capacitors’ current flows along the blue-marked path. The output voltage is
, with a capacitor, C1 connected across the input
(through S3)to maintain self-voltage balance.
Mode .
Mode is depicted in Fig 6. During the negative half-cycle, switches S1, S8, S10, and S12 are turned ON, directing the load current along the red-marked conduction path and generating a voltage of
at the load terminals. Capacitor C1 discharges through the load, increasing the output voltage to
.
Mode is depicted in Fig 7. Switches S2, S8, S7, S6, S9, and S12 are turned ON, causing capacitor C3 to discharge during the negative cycle, generating an output voltage of
. The load current follows the conduction path indicated in the red line. Simultaneously, the DC supply is connected to capacitors C1 and C2 (blue highlighted circuit), charging it (via S3, S5)
.
Mode .
Mode is depicted in Fig 8. Switches S1, S8, S7, S9, and S12 are turned ON, causing capacitors C3 and C1 to discharge during the negative cycle, generating an output voltage of
. The load current follows the conduction path indicated in red.
- (c) Voltage Balancing mechanism of capacitors
During one fundamental cycle of the load voltage, the capacitor charges to
at voltage levels of 0,
,
,
, while it discharges at
,
. Similarly, a capacitor
charges to
at voltage levels of
,
,
, while it discharges at
. Capacitor
charges at
and discharges at
. This continuous charging and discharging process occurs over one fundamental cycle. The series/parallel approach described in [23] can be used to charge and discharge the capacitors in the PT. Figs 2–8 depict how the capacitors charge and discharge to generate the various voltage levels and their switching pattern is summarized in Table 1. This ensures automatic self-balancing of the capacitors, stabilizing
and
, and
at
.
- (d) Guidelines for the Selection of the rating of a capacitor
This subsection represents a critical aspect of the proposed SC-based inverter topology. Numerous factors, including the type of connected load, peak load current (), and maximum discharge duration
), influence the choice of capacitor ratings. In light of this, the charge
released by the
capacitor during operation can be mathematically expressed as [5]:
Consider the worst-case scenario, (i.e., for pure resistive load [23]), maximum discharge can be expressed as:
Hence, the required capacitance values are obtained as:
Where, represents the charge variation of capacitor (
) during the charging/discharging interval, and
denotes the allowable voltage ripple across capacitor (
).
- (e) Analysis of leakage current
Fig 9 illustrates a typical TLI configuration [14]. The overall CMV is defined by [16] as:
Where : and
denotes the voltage difference between node ‘a’ and ‘b’ w.r.t PV module’s neutral point ‘N’. And
: parasitic capacitance of the PV module.
The leakage current can be illustrated as
In this TLBSCT, ,
,
. So
therefore,
is zero.
3. Modulation pattern
To ensure smooth switching operation in MLIs, various modulation strategies have been developed, including both low and high switching frequency PWM techniques. Figs 10–13 display the switching logic for the PT. In this control strategy, the modulating signal (fr) is initially compared with eight fixed reference levels (,1/3, 2/3, 1,
,-1/3, −2/3, −1). The resulting comparator outputs are processed through AND and EX-OR logic gates to generate the signals (P1, P2, P3) for the positive half cycle and (P11, P22, P33) for the negative half cycle, as illustrated in Fig 10 and Fig 11. Subsequently, the same modulating signal (fr) is compared with six high-frequency carrier signals, namely C1, C2, and C3 for the positive half cycle and C11, C22, and C33 for the negative half cycle, as depicted in Fig 12 and Fig 13. This comparison produces the signals q1, q2, q3, q11, q22, and q33. These signals, together with their complementary versions, are then applied to separate AND gates along with (P1, P2, P3) and (P11, P22, P33). As a result, the intermediate gating signals X1, x1, X2, x2, X3, x3, X11, x11, X22, x22, X33 and x33 are obtained. Finally, all of these signals are combined using OR gates to generate the final gate pulses required for operating switches (S1) to (S12). Fig 14 depicts output voltage levels obtained by the implemented modulation scheme.
4. Losses analysis
A SCMLI experiences the following losses, namely: conduction and switching and capacitor losses [14,16,17]. Fig 15 depicts the waveforms of voltage and current during switching with overlapping characteristics.
- (a) Power losses in capacitors
The power losses due to capacitor ripples and equivalent series resistance (ESR) are expressed as:
- (b) Switching Power Losses: In switching processes of a power switch, there are switching losses due to inherent delays. Therefore, the power dissipated while the device turns on and off can be expressed as follows [14]:
Similarly, the turn-off power losses in terms of voltage and current can be expressed as
Hence, the total switching losses of a power switch can be obtained as
- (c) Conduction Power Losses: The conduction loss of the transistor and diode of a particular power switch are obtained as [16]:
The following practical switching parameters have been used for the PT Table 2
5. Result discussion
The conceptual design of the PT has been verified through MATLAB simulations and tests performed on a laboratory prototype. The parameters employed for both evaluation methods are listed in Table 3.
- (a) Simulation investigation
Fig 16 presents the steady-state behavior of the proposed TLBSCT. It can be seen that the circuit delivers a 7-level waveform reaching a peak of 150 V, while the capacitor voltages stay automatically regulated around their intended reference values. When the PT is subjected to sudden variations in load and frequency, as illustrated in Fig 17 and Fig 18, the output voltage and the SC voltages remain stable. This confirms that the inverter maintains reliable performance under dynamic operating conditions.
Fig 19 shows the shifts of the modulation index (M) from 0.95 to 0.75 and from 0.75 to 0.5. It is found that the decrease in the “M” results in a decrease in the magnitude of output voltage and output current, respectively. However, the PT can still maintain the voltages of SCs stable and exhibits good capacitor self-balancing performance under diverse modulation settings. Also, as shown in Fig 20 and Fig 21 are the distribution of power loss among the PT switches respectively.
- (b) Experimental study
The feasibility of the PT has been demonstrated through tests carried out on a laboratory-built prototype. The module underwent testing under diverse conditions to assess the inverter’s performance. Figs 22 depict the experimental setup along with the corresponding outputs observed under different scenarios.
Fig 23 shows the waveforms of the R-L load in a steady-state condition. The uniform voltage across all three capacitors indicates effective voltage balancing. The waveforms for a change in RL load are shown in Fig 24. Output voltage comprises 7 levels with each level being 50V. The boost ratio is achieved to be 3, which indicates that the PT has the ability to provide an output of a maximum 150 V.It is seen from Fig 25 that the output voltage levels are consistent and not impacted by the frequency fluctuations as the switching frequency varies from 200 Hz to 2000 Hz. Moreover, the capacitor voltages are self-balanced, hence allowing stable operation for variations of switching frequency.
The inverter output is changed from 7-levels to 5- levels and subsequently to 3- levels as the M is changed (0.98 to 0.6 then to 0.3) as shown in Fig 26. This demonstrates that the PT can consistently generate a broad spectrum of voltage levels across a variety of modulation index values. Figs 27–30 show the voltage and current stresses of each switch. The voltage stress on switches is found to be below the load voltage. Figs 31 and 32 show the Capacitor, diode voltage and current. Moreover, the leakage current is observed to be zero as shown in Fig 33. The load versus efficiency curve has been plotted and the efficiency is seen to peak at about 200W in Fig 34. Voltage and current results from the THD analysis are displayed in Figs 35 and 36. The test outcomes demonstrate that the inverter performs well in steady state and shows strong dynamic behavior when responding to changes in its input conditions.
- (c) Grid-connected mode:
When connected to the grid, this mode allows the inverter to inject a sinusoidal current that is in synchronization with the grid voltage and has minimal harmonic distortion. Using a Proportional-Resonant (PR) controller, which guarantees zero steady-state error under sinusoidal reference conditions and gives a high gain at the fundamental frequency, the PT improves power quality and achieves precise current tracking [24]. The Proportional-Integral-Derivative (PID) controller’s transfer function is given by:
The parameters ,
denote the proportional gain, the infinite gain, and the resonant frequency, respectively. These parameters are critical for defining the behavior of the controller towards variations, the amplification at the desired frequency and the bandwidth around the resonant point.
To confirm the appropriateness of the PR controller for grid-connected operation, the suggested system was experimentally investigated using a scaled-down prototype. The parameters used in the test setup are given in Table 4 and the corresponding experimental findings are shown in Fig 37. The inverter generates a seven-level output waveform, with a peak amplitude of 400 V. Moreover, the experimental results demonstrate that the PT provides 0.3 kW active power and the grid voltage and current are in phase. This phase alignment verifies that the inverter operates at a unity power factor. Overall, the findings confirm that the PT performs effectively and maintains dependable operation under grid-connected conditions.
6. Comparative assessment
Several inverter topologies that have been reported previously are compared with the PT in Table 5. The topologies are evaluated based on key design and performance parameters including efficiency, TSVpu, MBV, NSW, NC, ND, Ndri, and gain.
The PT uses fewer switches than the topologies described in [9,36], and [19], which each have 14–16 switches. Despite the fact that some designs, like [7] and [15], employ just 6 switches, and [22] and [28] use 7 switches, these designs sacrifice other crucial features like efficiency, diode count, or voltage stress. The PT outperforms the competition while keeping the number of switches balanced, as shown in [4,6,12,20], and [24].
In comparison to topologies [6,7,12,15], and [20], which have 4 capacitors, the PT employs just 3 capacitors. The circuit complexity, cost, and capacitor voltage balance difficulties are all reduced as a result of the lower capacitor count. Minimal capacitor usage is achieved in a few of the topologies, including [4,9,36,21–23], and [27], but these topologies typically display reduced efficiency or increased voltage stress.
The PT uses just one diode, which is much less than the four diodes needed in [7,12,15], and [20], as well as the two diodes used in [35,11,10,22,24], and [28]. Conduction losses are reduced and the converter structure is simplified by using a lesser number of diodes.
With 12 driver circuits, the PT is similar to topologies [6,12], and [24] and has the same number of switches. Some topologies, such those in [35,11,22], and [28], have lower gain or higher voltage stress, but fewer drivers are needed for them. The increased voltage boosting capability and greater efficiency of the driver in the PT make it justified.
Several existing topologies have lower TSVpu values than the PT (6.66 vs. 7.33, 7.50, 8.66, 9.33, 10.66, and 7.30, respectively) [35,6,7,11,20,21,28] (7). Despite having somewhat lower TSVpu values, topologies like [4,9,36,12,14], and [19] either have a higher number of switches needed or are less efficient.
In comparison to references [35,6,7,15], and [23], where the maximum blocking voltage (MBV) falls between 3 and 6, the PT’s MBV of 2 is lower. Reliability is improved as a result of reduced voltage stress on switches. Although some topologies manage to get an MBV of 1, these designs necessitate additional switches or offer reduced efficiency and gain (for example, [9,11,12,36,10], and [14]).
Like most reported topologies, the PT yields a voltage gain of 3. This includes topologies [4,5,35,7–9,36,12,15,23,24,27], and [28]. In addition, it achieves better results than topologies [11,10,14,20,21], and [22], which provide a lesser increase of only 1.5. A larger gain of 4 is achieved by topology [6], but it comes at the cost of more capacitors and higher TSVpu and MBV.
The removal of leakage current is another significant benefit of the PT. In keeping with previous research [35,5,11,15,20,24], the PT is well-suited for safe and high-performance power conversion applications due to its nearly negligible leakage current. On the other hand, leakage current performance is not reported by several topologies, including [4,6–9,36,12,10,14,19,21–23,27], and [28].
When compared to all other documented topologies, this one outperforms them all (97.65%, (5) 97.7%, (7) 97.62%), (22) 97.5%, (23) 97.6%). Reduced power losses and improved overall energy conversion capabilities are demonstrated by the greater efficiency of the suggested design.
7. Conclusion
A new seven-level three- TLBSCT for the grid-connected photovoltaic application is proposed in this study. The PT possesses many desirable advantages such as zero leakage current, decreased component count, lower voltage stress across semiconductor devices, voltage boosting capability and intrinsic capacitor self-balancing operation. The operating modes, the parameter selection and the control approach of the PT are examined in detail. Furthermore, a comprehensive comparison with recently proposed TLIs demonstrates that the proposed design is better in terms of performance and efficiency. The simulation and experimental studies under various loading circumstances show the effectiveness and practical viability of the TLBSCT. The benefits of the PT are suitable for solar PV coupled to grid applications.
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