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A compact wideband Wilkinson Power Divider topology for arbitrary N-Way outputs

Abstract

This work presents a compact Wilkinson power divider (WPD) topology capable of realizing arbitrary 1 × N equal power divisions without requiring crossovers or unrealizable high-impedance lines. The design combines both equal and unequal power division stages, enabling flexibility for even and odd numbers of outputs. Power divider units with 1:2 and 1:3 ratios are used as the basis for constructing higher-order N-output WPDs. Miniaturization is achieved through tapered-line impedance transformers, limiting the maximum line impedance to 103 Ω within fabrication constraints. A two-stage 1 × 3 divider is designed, fabricated, and tested at 2.4 GHz on a microstrip platform. The prototype demonstrates an 85% effective bandwidth with amplitude imbalance within ±0.2 dB, and phase imbalance less than ±2.5°. Compared to conventional topologies, the present approach achieves up to 58% size reduction while maintaining wideband performance. This work is highly suitable for M × N high-performance, efficient, reliable, and scalable beamforming network architecture. This work supports SDG 9 Industry Innovation and Infrastructure by enabling compact, scalable, and high-efficiency microwave components for advanced communication and infrastructure systems.

1. Introduction

Power dividers and combiners are fundamental passive microwave components widely employed for signal distribution and combination in applications such as RF beamforming, phased arrays, mixers, and power amplifiers [1]. The conventional Wilkinson power divider (WPD) [2] employs two quarter-wavelength transmission lines at the design frequency f0. While simple in structure, this approach leads to large circuit sizes, especially at lower frequencies. A single-stage WPD provides narrowband performance, whereas multistage extensions enhance bandwidth at the expense of increased printed circuit board (PCB) area. The number of stages is further constrained by fabrication limits on high-impedance lines.

To avoid the above problem for multiple outputs, a parallel combination of basic 1:2 WPD can be used for even N, whereas odd N requires one port to be matched, causing power loss. A hybrid of equal and unequal topologies can yield compact and wideband designs. Several microstrip-based approaches for an arbitrary number of outputs have been explored [313], including size reduction techniques using electromagnetic band gaps [3], high–low impedance resonators [4], and lumped components [5]. However, all of them suffer from a narrower bandwidth than conventional WPDs.

Multistage topologies are commonly used for wideband WPDs, but they usually result in large circuit sizes. Recent alternatives employ slot or parallel-strip lines [6] and lumped elements [79]. Miniaturized unequal WPDs have also been reported [1013] using few capacitors for matching and phase compensation [10], artificial and double-sided parallel-strip lines [11], stepped-impedance lines with resonators [12], and asymmetric resonators with coupled stubs and folded structures [13]. While these achieve notable size reduction, they become complex at high division ratios.

This article presents a modified WPD topology, which can be used to design and implement any WPD with an arbitrary number of outputs. It avoids crossovers and the limitations due to the implementation of high impedance lines. As shown in Fig 1, a basic 1:2 WPD with N = 2 and another 1:3 with N = 3, shown in Fig 2, are developed first. Then, any N is implementable based on these two basic units with components listed in Table 1.

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Table 1. Components required in N-outputs of present Wilkinson power divider unit for N > 3.

https://doi.org/10.1371/journal.pone.0352515.t001

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Fig 1. Schematic representation of unit -A (1:2 power division) of proposed WPD.

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Fig 2. Schematic representation of unit -B (1:3 power division) of proposed WPD.

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Various configurations from N = 4–8 are shown in Figs 3,4,5, 6 and 7, respectively. A lossless transmission line model is used for all the analysis. Advantages of the present approach compared to others are elaborated. Further, miniaturization is achieved by replacing quarter-wave transformers with tapered lines after each stage for 50 Ω matching. The maximum line impedance is limited to 103 Ω, remaining within fabrication constraints. As N increases, the design maintains practical impedance levels through the use of tapered impedance transformers, preserving fabrication feasibility. The taper dimensions, including taper length, width profile, and impedance transition ratio, were optimized through a combination of analytical estimation and full-wave EM simulations.

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Fig 3. Schematic representation of 1 × 4 WPD configuration.

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Fig 4. Schematic representation of 1 × 5 WPD configuration.

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Fig 5. Schematic representation of 1 × 6 WPD configuration.

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Fig 6. Schematic representation of 1 × 7 WPD configuration.

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Fig 7. Schematic representation of 1 × 8 WPD configuration.

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2. Analysis and design of WPD units A and B

The 1:3 power divider (N = 3) is further analyzed. While ABCD-parameter-based even- and odd-mode analyses are available in [14,15], the present work employs a simple impedance transformation-based even- and odd-mode analysis, which can be extended to the design of unequal power ratio. The corresponding even- and odd-mode equivalent circuits are shown in Fig 3.

For even mode analysis, a condition to ensure no current flows through resistor RN1 is

(1)

If the power division ratio is P2/P3 = 1/k, to maintain the symmetry, the impedance at node b is

(2)

To minimize the impedance transformation ratio for a given power division and thus to maximize the bandwidth, the optimum value of impedances should be chosen, such that their geometric mean is equal to Z0 [16]. Therefore, even-mode impedances at node and are

(3)

and

(4)

Now, the condition for impedance matching at node and is

(5)

Since a quarter-wave transformer is used, therefore

(6)

The condition for maximum power transfer at node and is

(7)

Therefore, from (5) and (6), the input impedances at node and are

(8)

and

(9)

Again, applying the quarter-wave transformer theory in both parallel microstrip lines with characteristics impedances ZN1 and ZN2, the respective expressions are

(10)

and

(11)

Similarly,

(12)

and

(13)

Since, in the odd-mode, all current flows through RN1 due to a short-circuit at one end of ZN1 of length 90o, the conditions for maximum power transfer at the node and are

(14)

and

(15)

Hence,

(16)

and

(17)

and

(18)

Therefore, design steps to implement a 1:3 WPD with N = 3, shown in Fig 2, are (i) decide the power division ratio for first stage, i.e., 1:2 (ii) calculate Z31 and Z32 using (8) (iii) calculate ZQ31 and ZQ32 using (9) (iv) calculate R31 using (12) (v) for second stage with 1:1, repeat steps (i) to (iv) to calculate Z21, Z22 and R21 to implement unit-A, shown in Fig 1. (vi) place unit-A at the output port, with double power, of first stage. (vii) design, optimize and fabricate the circuit. For example, calculated parameters of for 1 × 3 WPD unit using present topology are Z21 = Z22 = 70.7 Ω, Z31 = 103 Ω, ZQ31 = 59.45 Ω, ZQ32 = 42.04 Ω, Z32 = 51.5 Ω, R31 = 106.05 Ω, and R21 = 100 Ω.

To miniaturize WPD units, in the present topology, QWTs with impedances ZQ31 and ZQ32 are realized using small tapered microstrip lines to match Z31 and Z32 with Z0, without influencing other performance aspects. With the longitudinal electrical length reduced by 80°, the overall size of the modified 1 × 3 WPD becomes about 70% of a conventional WPD with QWTs. Furthermore, for all configurations having an even number of outputs, the first-stage power division ratio remains 1:1, and a single unit A is sufficient to design a WPD with binary outputs. Conversely, for configurations with an odd number of outputs, the first-stage power division ratio becomes [(N + 1)/2]: [(N-1)/2].

3. Comparison with Conventional N – way WPDs

Various possible N-way equal power WPD topologies as cases A, B and C, are shown in Fig 8,9 and 10, respectively. Comparison graphs of various figure of merits such as insertion loss (I.L.), return loss (R.L.) and isolation (Iso.), bandwidth (B.W.) required for N = 3–8, for all topologies, are shown in Fig 11. Similarly, graphs for overall circuit size and maximum line impedance required for N = 3–8, for all topologies, are shown in Fig 12. For effective bandwidth calculation, output power magnitude imbalance of ± 0.5 dB and both R.L. and Iso. Magnitudes greater than 15 dB are considered.

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Fig 8. case A: conventional single stage 1 × N equal power WPD topology.

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Fig 9. Case B: conventional multistage 1 × N equal power WPD topology.

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Fig 10. Case C: conventional multistage unequal power 1 × N equal power WPD topology.

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Fig 11. Comparison of I.L., R.L., and Iso.

B.W for all four topologies.

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Fig 12. Comparison of max. impedance requirement and circuit size for all four topologies.

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The unrealizable impedance requirements of case A beyond 1:6 restrict its use to a maximum of 36 output ports. Additionally, multiple crossovers lead to higher fabrication complexity and larger overall size. Nevertheless, the Iso. Bandwidth improves because of the high isolation resistor, while I.L. and R.L. bandwidths degrade rapidly as outputs increase. Although case B provides comparable bandwidth and impedance requirements, its binary output property results in excessive circuit size with significant unused PCB. For example, a 1 × 9 WPD using this approach contains nearly 50% unused PCB area. Extremely high and low impedance requirements, impractical isolation resistor values, and exponential one-dimensional circuit growth are the key limitations of case C.

The present approach overcomes the limitations of traditional topologies, enabling any number of outputs with easily realizable maximum impedance and practical resistor values without degrading effective bandwidth. Additionally, the entire PCB area is efficiently utilized. For comparison with conventional designs, the limiting case of case A, i.e., N = 6, is considered, where impedance requirements for A, B, and C topologies are 122.5 Ω, 70.7 Ω, and 183.2 Ω, and circuit sizes with tapered sections are about 9.5 cm², 25.8 cm², and 36.2 cm², respectively. For the proposed approach, these values are 103 Ω and 19.4 cm², respectively. Thus, miniaturization of 25% and 50% is achieved compared to cases B and C, respectively. Although the circuit size for case A is only 50% of the proposed WPD, its impedance requirement is unrealistically high.

4. Design, Fabrication and Measurements

The full wave simulation tool Ansys HFSS is used to obtain the final physical dimensions of power dividers. A 20-mil thick RO4003C substrate with εr = 3.55, and tanδ = 0.0027 is used for simulations and fabrications. In the present WPD, the first and second stages are designed for 1:2 unequal and 1:1 equal power division, respectively. For verification of basic units, one 1 × 3 WPD is designed with C shape geometry instead of the quarter wavelength arms, along with optimized tapered length to achieve miniaturized WPD. As a result, the overall circuit size of the modified 1 × 3 WPD unit is 5.62 cm2, while it is 13.32 cm2 using standard quarter wavelength lines. Fig 13 shows the microstrip line layout of the present equal power WPD circuit. Various dimensions are mentioned in the figure caption. The present divider is purposely designed for the phased array application; therefore, at port 2, an additional 50 Ω line of 90° electrical length is added. As a result, the output amplitude at port 2 is reduced. However, equal phase at each output is maintained, which is necessary for phased array applications. A prototype two-stage 1 × 3 Wilkinson power divider in microstrip line technology is fabricated for 2.4 GHz operation, shown in Fig 14.

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Fig 13. Layout of present 1 × 3 WPD unit (w50 = 1.14, w103 = 0.15, w51.5 = 1.0, w70.7 = 0.6, l50 = 14; unit: mm).

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Fig 14. Fabricated prototype of present 1 × 3 WPD unit.

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Fig 15 and 16 show calculated, simulated, and measured reflection, transmission coefficient, and isolation plots of WPD, respectively. Measured minimum 15 dB return loss and at least 17 dB isolation between all output ports are achieved over the frequency range of 1.2–3.0 GHz. At the center frequency of 2.4 GHz, these values are a minimum of 20 dB and 22 dB, respectively. Calculated, simulated and measured phase difference and amplitude imbalance between output ports are plotted in Fig 17 and 18. However, a different phase difference slope is seen due to the additional transmission line at port 2; the measured phase difference at the design frequency is within ± 2.5°. Amplitude imbalance is well within ± 0.2 dB over 1.2–3.6 GHz, while it is maximum ± 0.1 dB at 2.4 GHz. However, measured magnitude variations at port 2 deviate from simulated ones; it is well within the acceptable range. The rectangular size occupied by one unit of the present 1 × 3 WPD is 0.13λ2g at mid-band frequency.

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Fig 15. Calculated, simulated and measured reflection coefficient of the present 1 × 3 WPD unit.

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Fig 16. Calculated, simulated and measured isolation of the present 1 × 3 WPD unit.

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Fig 17. Calculated, simulated and measured phase difference of the present 1 × 3 WPD unit.

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Fig 18. Calculated, simulated and measured amplitude imbalance of the present 1 × 3 WPD unit.

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Performance of the proposed structure is compared to other designs and listed in Table 2. It shows that the present WPD delivers excellent performance with a compact PCB area among all except single-stage WPD configurations [9,12], and [13]. However, single-stage equal power division units in [4,5,8], and [12] offer higher isolation; all other designs offer comparable isolation response. Excellent bandwidth response is shown by the present design except [6], using a smaller-sized circuit. Moreover, the present work demonstrates the least complexity, even for an arbitrary number of outputs across all available designs.

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Table 2. Comparison with recent wilkinson power dividers works.

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5. Conclusion

A generalized Wilkinson power divider topology for arbitrary N-way equal power division is presented here. By combining unequal and equal power division stages, the design achieves compactness, wide bandwidth, and scalability without relying on impractical impedances or unused matched ports. The approach offers significant miniaturization through tapered-line transformers, yielding up to 58% reduction in PCB area compared to conventional multistage topologies, while maintaining an 85% effective bandwidth. A 1 × 3 prototype fabricated at 2.4 GHz confirms the theoretical and simulated results. In the proposed topology, the tapered impedance transformers play a significant role in bandwidth enhancement by providing smoother impedance transitions between interconnected divider sections, thereby reducing reflections over a wider frequency range. The present WPD topology is well-suited for integration in modern phased arrays, wireless LANs, and broadband RF front-end systems. However, the present work focuses on equal power division, the design methodology inherently supports the incorporation of unequal power division stages through appropriate selection and cascading of divider units. This feature enables realization of non-uniform excitation distributions required for sidelobe level reduction techniques such as Taylor, Chebyshev, or other amplitude tapering methods. In principle, the proposed topology is extendable to mm-Wave frequencies due to its transmission line based closed form expression. However, in mm-Wave range, few practical challenges such as pronounced losses, sensitive fabrication tolerance and advanced EM optimization to maintain precise amplitude and phase balance across the output will arise. Despite these challenges, the proposed topology possesses several favourable characteristics for mm-Wave adaptation, including the absence of crossovers, the avoidance of unrealizable high-impedance lines, and a compact, scalable structure. These features can simplify layout complexity in dense multiport beamforming networks.

Acknowledgments

The authors would like to thank Mr. Jagannath Mukhi of the Dept. of E & ECE, IIT Kharagpur, for fabricating the structure.

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