Figures
Abstract
This paper presents a design of fully differential chopper amplifier employing the flipped voltage follower (FVF) adaptive biasing technique, focusing on its potential use in biopotential recording applications. The suggested architectural OTA incorporates self-cascoded current mirrors (SCCMs) as the active load to achieve a substantial output swing. The FVFs based adaptive biasing approach for the differential input stage boosts extra current and enhances gain and dynamic characteristics. The chopper amplifier attains a common mode rejection ratio (CMRR) of more than 100 dB through the strategic utilization of chopper modulators and pseudo-resistors. Additionally, this device exhibits characteristics such as accurate and stable gain, high input impedance, and a compact physical footprint. The present study also includes a comparison between the suggested structure and the bio-potential amplifiers discussed in the existing literature. This comparison is based on key metrics such as gain, input referred noise (IRN), CMRR, and input impedance (Zin). The proposed structure yielded a gain of 63.72 dB, an IRN of 0.07nVrms, a CMRR of 127.97 dB and a Zin of 1.54 GΩ. The bio-potential chopper amplifier under consideration was constructed and simulations were performed by utilizing the Cadence Virtuoso Spectre simulator tool at 180 nm CMOS technology node.
Citation: Kasipogula BR, Komanapalli G (2024) A chopper amplifier with adaptive biasing OTA for biomedical applications, featuring high gain and CMRR. PLoS ONE 19(11): e0313423. https://doi.org/10.1371/journal.pone.0313423
Editor: Hugh Cowley, Public Library of Science, UNITED KINGDOM OF GREAT BRITAIN AND NORTHERN IRELAND
Received: February 1, 2024; Accepted: October 23, 2024; Published: November 13, 2024
Copyright: © 2024 Kasipogula, Komanapalli. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Data Availability: All relevant data are within the manuscript and its Supporting information files.
Funding: VIT-AP University.
Competing interests: The authors have declared that no competing interests exist.
Introduction
A signal refers to a tangible occurrence that conveys data or knowledge. The utilization of bio-electrical signals can facilitate the acquisition of data about a biological system being investigated [1]. Neural signals exhibit a diverse range of amplitudes, spanning from tens of micro-volts to several milli-volts. These signals also possess distinct bandwidths, which are shown in Table 1. In this particular scenario, a crucial component of the brain recording system is an appropriate amplifier capable of effectively amplifying low-frequency and low-amplitude signals. It must also effectively counteract the substantial random DC offset, reaching several hundred millivolts, that arises at the interface between the electrode and tissue.
In order to adequately amplify these biological signals of low amplitude, it is necessary to use appropriate amplification techniques while simultaneously mitigating the presence of noise [2]. Three primary strategies employed to eliminate low-frequency components include loading the recording site with a high-value resistor, using active feedback for low-frequency suppression, and utilizing a capacitive feedback network [1]. Analog circuits that utilize transistors functioning in the subthreshold region exhibit reduced energy consumption during active operation and lower leakage power dissipation compared to those operating in the strong inversion zone. The performance attained in the subthreshold area is deemed sufficient for many energy-constrained applications and similar scenarios. Therefore, it is necessary to develop amplifiers specifically designed for biomedical applications that can effectively attain high time constants and high gain. The measurement of brain signals in portable bio-medical monitoring systems is significantly affected by different interfering signals, including electrode offset, flicker noise (1/f), and powerline interference. Hence, to ensure optimal performance, it is imperative to limit the power consumption of the gadget [3].
The design of low-power systems is an essential undertaking that necessitates the constant development of innovative solutions in order to meet the expectations of the industry. In the given environment, the operational transconductance amplifier (OTA) retains its significance as a pivotal component owing to its adaptable nature across a diverse range of applications. Additionally, OTAs possess high-performance characteristics including overall transconductance (Gm), gain-bandwidth product (GBW), slew rate (SR), settling time (ST), area, input-output swing, and noise [4] and they can work within the limitations of low voltage and low power.
This work presents “flipped voltage follower (FVF)” as a potential solution to address some limitations seen in the field [7–9]. Previous studies have demonstrated the utilization of several iterations of this particular cell to achieve low-voltage and low-power functioning. This research delves into an category of Class-AB OTA (Operational Transconductance Amplifier) circuit referred to as variable-mirror amplifier (VMA), highlighting their pivotal role in the development of chopper amplifier. These VMAs are constructed using single-stage topologies that use non-linear current mirrors. However, this paper enhances the concept by incorporating several additional features. These include an extension to the weak inversion operation, the introduction of a new auxiliary biasing circuit to enhance control over peak currents, the derivation of analytical expressions for the maximum slew rate, the provision of a comprehensive set of parametrized curves to demonstrate the design flexibility of the VMA topology, and a thorough analysis of settling time to optimize power consumption in switched-capacitor (SC) circuits [10].
The utilization of the suggested VMA design ensures that Class-AB dynamic peak currents are exclusively directed toward the output transistors. In addition to its inherent power-saving benefits, this single-stage design method effectively circumvents the current and area overheads often associated with frequency compensation techniques. Furthermore, it has the advantage of accommodating load-capacitance capabilities spanning several decades and is compatible with the quick on-off operation in SC circuits. Finally, it is worth noting that the suggested VMA family has a notable degree of technological and temperature insensitivity [11].
The input-referred noise of the amplifier can be mitigated by adjusting the size of the input devices or employing circuit methods, such as chopper stabilization, to minimize the impact of flicker noise. In the context of an action potential sensing application, chopper modulation is implemented at elevated frequencies. Therefore, to maintain the input impedance of the amplifier, it is necessary to perform chopper modulation of the input signal at the virtual ground of the amplifier [12]. The noise experienced at the recording location will be amplified as a result of the reduced input impedance of the amplifier, which is caused by the loading of the electrode impedance. In practical applications, it is important to ensure that the overall input-referred noise of the amplifier remains lower than both the extracellular neuronal background noise and the background noise originating from the electrodes.
In this study, a pseudo-resistors (RP) [1] with resistance values in the range of hundreds of GΩ is designed. This design takes into account the issue of leakage via the reverse-biased pn junctions, which has a detrimental effect on the performance of the RPs.
This research incorporates a cutting-edge design featuring a superclass AB OTA [13]. The design includes self-cascode current mirrors (SCCM) and an adaptive biasing approach based on an FVF. The presented OTA is modified to operate with low voltage and low power consumption, aiming to enhance slew rate, DC gain, gain-bandwidth product, and CMRR while minimizing static power dissipation.
The present paper is structured in the following manner: The chopper amplifier section provides an overview of the proposed architectural design and offers a comprehensive analysis of the significant parameters of the amplifier. The implementation and design of the high-gain amplifier are presented in the OTA circuit section. The next section presents a pseudo-resistor and chopper modulation technique for noise analysis and reduction. The results section comprises various simulation results performed using Cadence Virtuoso. Finally, concluding remarks of the work is presented as separate section.
Architecture of chopper amplifier with adaptive biasing technique
The proposed system architecture is depicted in Fig 1. It comprises a low noise chopper modulator, a single-stage suggested OTA with FVF topology denoted as ‘A’, and a capacitive feedback loop utilized for establishing the mid-band gain. Additionally, RPs are employed to provide substantially increased resistance.
The chopper modulation technique aims to improve the CMRR of the differential amplifier and mitigate the presence of flicker noise in the CMOS transistors. The input chopper, without altering the common-mode signal, enables the core amplifier to treat it as a standard input. The basic amplifier converts the common input into differential output by the utilization of the common mode gain. However, the differential mode output voltage is altered by the output modulator due to the non-zero gain of the common mode amplifier. As a result, it is possible to remove it by the same process used for filtering out flicker (1/f) noise and input offset voltage [14].
Traditionally, AC-coupled amplifiers are implemented by including a DC-blocking capacitor in series at the input. However, the attainment of extremely low cut-off frequencies sometimes necessitates the use of quite large capacitors. This is a drawback in bio-potential recording applications because of the substantial silicon area occupied by these capacitors. The impedance seen at the input of a current mode chopper-stabilized amplifier may be approximated as 1/(2πfchopCin), where fchop represents the chopping frequency occurs and Cin denotes the DC-blocking capacitor connected in series [15, 16].
A feasible alternative to active-RC integrator is the utilization of MOSFETs functioning within the linear operational range as a replacement for resistors. In this particular scenario, the MOSFETs are commonly referred to as RPs. In the context of weak inversion, it has been observed that RPs can exhibit a significant bias-induced effect, leading to the manifestation of remarkably high channel resistances. The resistances RPs, in conjunction with integrated capacitors, can attain the notably extensive time constants necessary for applications involving very low frequencies. However, it is important to note that achieving this requires the utilization of exceedingly low bias currents [17].
It is evident that best possible performance, it is imperative to employ a completely differential amplifier that incorporates symmetrical feedback. However, it is possible to efficiently regulate the gain by using just one feedback line. The analytical circuit shown in Fig 1 achieves balanced feedback paths by using matching resistors, labeled as Rf.
The closed-loop transfer function of the amplifier [18] can be expressed as:
(1)
The comprehensive breakdown of the aforementioned equations can be found in Appendix A. The Cin/Cf ratio is a quantitative metric that may be employed to determine the mid-band gain, denoted as (AM) and Gm represents the transconductance. The lower cutoff frequency may be determined by the formula 1/(RfCf), where Rf represents the feedback resistance and Cf represents the feedback capacitance. The analysis shown above does not consider the electrode resistance (Rs) because of its negligible impact compared to the feedback component (Rf). The contribution of noise from the Rf and OTA to amplifiers is significantly reduced as a result of the extremely narrow bandwidth [19].
The FVF-OTA rejects the input and output common-mode voltages, preventing them from entering. Similarly, the output voltage is dictated by the offset voltage. The circuit being discussed utilizes asymmetrical feedback and utilizes offset voltage to affect Vout uniquely, resulting in the presence of offset voltage in output. The deficiency of symmetry in the differential amplifier causes imbalances in the operating points of its internal nodes, resulting in a reduction in the alignment of open-loop gains. Although CMRR may not be a major issue with single-ended inputs, the research highlights a considerable trade-off in CMRR when nonsymmetrical feedback is used.
By leveraging the aspect ratio correlations outlined in Table 2, we can derive the amplifier specifications necessary for our requirements. When designing a bio-potential amplifier, it is essential to consider the trade-offs between noise and power consumption. The selection of device size is a deliberate process aimed at optimizing amplifier performance metrics, including input-referred noise, low-frequency gain, input impedance, and bandwidth, with the ultimate goal of achieving the optimum amount of channel inversion.
Circuit architecture
The implementation of a class-AB OTA based on the FVF adaptive biasing circuit (ABC) technique is depicted in Fig 2. The ABC consists of a pair of input differential transistors, M1 and M2, which are matched and cross-coupled by the two DC-level shifters. The implementation of each DC level shifter involves the utilization of two FVFs [13], which are comprised of transistors M1A, M2A, M1B, M2B, and a current source Ib. The active loads in this system are realized through the use of SCCM architecture. The driver transistors, namely Ma3–Ma8, are biased close to the linear region. On the other hand, the cascode transistors, denoted as M3–M8, operate either in the linear region or the saturation region, depending on the voltage bias applied to their gates. The transition occurring between the linear and saturation regions of the transistors results in the intended amplification of current [13, 20, 21].
The traditional class A OTA can evolve into a superclass AB OTA through the replacement of the constant bias current source (Ib) with an ABC. The SCCM architecture has been implemented utilizing a class AB PMOS differential pair. The ABC allows for a significantly higher current to be delivered compared to the quiescent current when a large differential input signal is present. This circuit is specifically engineered to provide minimal quiescent currents to transistors M1 and M2, while automatically boosting the bias current when substantial differential input signals are detected. To elevate current amplification and optimize output swing, the input differential pair is replaced with SCCMs [22].
The class AB configuration in OTA, demonstrates significantly increased current output when exposed to a substantial differential input voltage, exceeding its quiescent currents. The tail is bifurcated into two transistors (M1 and M2), each linked to the source terminal of the differential pair and the source degeneration active load. Positioned between the source terminals of the differential pair is a symmetrically configured source degeneration active load comprised of transistors M3 and M4. Importantly, this load is individually forward-body-biased through the buffered input voltage signals Vp and Vn [5, 23].
The gain of the suggested OTA is determined by analyzing the analog low-frequency signals. In the depicted diagram, Vp and Vn denote the absolute values of the input voltages that are applied at the gate terminals of MOSFETs M1 and M2, respectively. represents the transconductance of the Kth MOSFET, where K equals to 1, 2, 1A, 2A, 1B, and 2B.
(2)
In the given context, μK represents the carrier mobility, W/L is the transistor aspect ratio, and represents the bias current of the Kth transistor [13]. The disregard of channel length modulation in Kth transistors is done to simplify the mathematical formulas.
(3)
The overall gain of the OTA denoted as and detailed analysis of the above equations is available in Appendix B. The variables
and
represent the effective transconductance and effective output resistance, respectively, of Pth self-cascode transistors (MP and MaP). The value of P can range from 3–8. In order to enhance the range of maximum output, the output transistors M4 and M8 are interconnected in a conventional common-source design. Under quiescent circumstances, the transistors M5, M6, M7, and M8 function within the subthreshold region.
Pseudo-resistor
The fundamental unit of the floating pseudo-resistor (RP) in Fig 3 utilizes transistors MP1 and MP2 to function as a resistor. These transistors are connected in series to augment the overall resistance. The transistors MP3 and MP8 are utilized as the biasing circuit with a current source Ib. The achievement of higher resistance values, denoted as RP, at low cutoff frequencies. These resistors exhibit a notable advantage in terms of occupying less physical space compared to passive resistors. It is worth noting that previous RP values were biased at the subthreshold inversion point. The voltage follower, specifically the MP1–MP2 configuration, serves to transform a voltage that is referred to ground into a voltage reference that is floating [1].
In the present work, the resistance value attained with the topology is described when the RP operates in the subthreshold region.
(4)
The symbol ϕt represents the thermal voltage, and the aspect ratios W/L of the transistors MP1 and MP2, respectively. Based on the findings, it is evident that there exist two distinct design techniques that might be employed to get a significant value of RP. Initially, it is imperative to minimize the bias current, which can be accomplished by using a very precise current reference and/or employing down-mirroring techniques. Additionally, the ratio between the aspect ratios of MP1 and MP2 must be significant [24].
The adjustment of the aspect ratios necessary for the design was achieved by the utilization of a combination of series connections of transistors. To enhance resistance and linearity, a series connection was established between RPs biased by distinct voltage followers. It should be noted that the RP’s segments are biased using a sole current source (Ib) and a single reference transistor (MP1). Furthermore, it is unnecessary to assign individual Ib and MP1 to each segment of the RP, as demonstrated in reference, since the floating voltage remains constant throughout all segments [25, 26].
RPs are subject to significant constraints that stem from parasitic effects, including the direct current (DC) leakage and the capacitance of reverse-biased pn-junctions, along with the dispersed capacitance of the transistor channel.
Low noise chopper modulator
The block diagram depicted in Fig 4 illustrates the chopper circuit, which is readily built with MOS technology and it requires only four switches MC1, MC2, MC3, and MC4 for a complete differential chopper implementation. The passive chopper circuits directly take the input signal from the electrode and are considered to be noise-critical. The process of achieving signal sign inversion involves the straightforward alternation of the signal route by using a clock and its counter-phase. The utilization of the clock counter phase in dummy switches enables the cancellation of the main switch charge to a first-order approximation through the absorption and release of the dummy MOSFET charge [27].
In the field of CMOS technology, the utilization of MOSFETs offers a straightforward approach to implementing switches. The input chopper transforms a DC signal input into a square wave. The process of chopping entails the utilization of two polarity-reversing choppers to achieve accurate modulation and demodulation. The chopper configuration of four switches controlled by clock signals exhibiting two complementary phases, operating at a certain chopping frequency denoted as fchop. Following amplification, the output chopper performs demodulation on the square wave signal, resulting in the restoration of DC voltage. In the context of frequency analysis, the input chopper efficiently shifts the DC signal to the odd harmonics of the chopping frequency, and then the output chopper restores the high-frequency components to the DC level [28].
Typically, the act of chopping does not result in the introduction of additional noise, particularly when the choppers are situated at low-impedance nodes. In the given scenario, the primary source of noise may be attributed to the on-resistance of the input chopper. Therefore, by reducing this value to a sufficiently low level, the noise generated by it is rendered inconsequential.
Noise analysis of the chopper amplifier
Fig 5 illustrates the noise model of a chopper amplifier. The representation of the amplifier with noise may be equivalently expressed as a voltage source (Vn,IA) in series with a noiseless amplifier and a current source (In,IA) in parallel with the same noiseless amplifier [29, 30].
In the realm of designing low-noise amplifiers in CMOS technology, the primary sources of noise are commonly attributed to thermal noise and 1/f noise. This section will conduct a theoretical analysis of the impact of chopping modulation on the noise performance of an amplifier [30, 31]. The total input-referred noise power spectral density (PSD) is given by
(5)
(6)
where ZS is the impedance of the source. In the case of low frequencies and high input impedance, the dominant term in Eq 5 is the first term. The rearrangement of equation Eq 5 results in the addition of a thermal noise term, denoted as SN0, together with a low-frequency 1/f noise term as shown in Eq 6, where fc represents the corner frequency. Subsequently, the input noise of comparable magnitude is amplified by the voltage gain, denoted as A0, and subjected to modulation through the output chopper. The PSD of the output noise is obtained by summing the copies of the noise spectrum that are positioned at odd harmonic frequencies of the chopping frequency (fchop) [30, 32, 33].
(7)
(8)
The variable “fcutoff” represents the cut-off frequency of the amplifier. It is evident from Eq 8 that the noise level at the baseband is essentially equivalent to the thermal noise, SN0 when the amplifier’s bandwidth is significantly greater than the chopping frequency.
Simulation results
The evaluation and performance of the proposed switched capacitor chopper amplifier based on FVF-OTA design using a 180 nm CMOS technology node, was conducted with a chopping frequency of 30 kHz. The biopotential amplifier presented utilizes the FVF-OTA and employs a cascode current mirror to generate the gain and CMRR. The amplifier achieves a gain of 63.72 dB, effectively amplifying it within the frequency range of 0.1 Hz to 12.17 kHz. The circuit functions by utilizing 29.61 μW of power, while exhibiting an IRN of 0.07 nVrms. In depicted Fig 6 a simulated capacitive feedback amplifier has a layout design size of 0.009 mm2. The layout characteristics are achieved through the utilization of MIM-based capacitors.
The amplifier that was developed with input capacitance (Cin) of 3 μF, feedback capacitance (Cf) of 1 pF, and load capacitance (CL) of 3 pF. To imitate the functioning of the circuit, a sinusoidal signal is employed. This signal possesses an amplitude of 100 mV, a frequency of 100 Hz, and a DC offset of 50 mV, which is introduced to compensate for the electrode offset voltage. In order to analyze the behavior during startup and transient phases, it is necessary to replicate the transient response of the circuit across a reasonable time range, as depicted in Fig 7. The significance of Class-AB operation in low-frequency amplifiers is of utmost relevance owing to its capacity to offer both efficiency and linearity. Class-AB amplifiers are characterized in that each amplifying device operates for a duration slightly exceeding half of the input signal cycle. Their suitability for low-frequency applications require precise signal reproduction due to their ability to minimize crossover distortion. Additionally, it delves into the compromises involved in choosing the most suitable biasing point for class-AB operation, taking into account the balance between quiescent current and distortion performance.
Differential gain and CMRR indicate the amplifier’s effectiveness in rejecting common-mode signals. Incorporating the FVF adaptive biasing technique into the chopper amplifier makes it easier to maintain a steady state of operation. Consequently, CMRR and differential gain improved by limiting bias current fluctuations and reducing common-mode distortion. The closed-loop differential gain, common-mode gain, CMRR are measured to be 63.72 dB, -64.25 dB, and 127.97 dB respectively, as depicted in Fig 8. When the gain decreases by 3 dB, the frequency range spans from 0.1 Hz to 12.17 kHz, and the bandwidth is constrained.
The proposed architecture was employed to amplify and process biological signals, which are inherently of small amplitude. The reduction of flicker noise generated by the adaptive biasing of the FVF can be accomplished by employing filtering methods, such as the utilization of a low-pass filter or the application of noise cancelation techniques. The utilization of feedback control techniques in this context enables the stabilization of the amplifier performance and enhances its resilience against noise induced by the FVF adaptive biasing circuitry. Hence, the investigation of noise has been carried out by the utilization of simulation techniques. The measurements of input noise and output noise were obtained at levels of 159.847 and 0.77
, respectively, as depicted in Figs 9 and 10. The presented data illustrates the noise characteristics of has been improved for the circuit design under consideration.
The chopping technique does mitigates 1/f noise effectively, which is its primary advantage. However, the process introduces elements (switched capacitor resistance and high-value capacitors) that can increase input impedance Zin. Therefore, while it might seem that chopping should reduce the input impedance, the introduction of these components and their associated resistances actually results in an increase in the overall input impedance. As a result, the impedance in the FVF-OTA architecture typically exceeds 1.545 GΩ. Therefore, it has been implemented to minimize loading effects and increase input impedance to achieve the desired gain and CMRR performance.
Corner analysis involves simulations under different supply voltage corners to assess the amplifier’s response to supply voltage variations. It serves as a crucial tool to assess the effectiveness of adaptive amplifiers in preserving intended performance metrics under worst-case scenarios by consistently demonstrating performance in process, temperature, and supply voltage corners. The differential gain, and CMRR of the amplifier indicate a little deviation from the anticipated level, and various corners have been performed as shown in Figs 11 and 12, respectively. As depicted in the Fig 13, the offset voltage demonstrates a progressive rise throughout the frequency range of 1 MHz to 30 MHz, which can be attributed to common interference. Subsequently, it stabilizes within a gradual range once again. In order to comprehensively depict the behavior of offset voltage across the whole frequency spectrum of interest, it is imperative to incorporate a suitably broad frequency range within the plot. It will guarantee the most efficient frequency range for chopping, according to individual applications and performance criteria. The designed amplifier performance observes that Stand and FS corner frequencies exhibit somewhat sophisticated values compared to the simulated values.
Table 3 illustrates the performance metrics of the amplifier under examination, along with comparisons to findings from related studies. This comparison reveals that the suggested amplifier outperforms others in gain, CMRR, and exhibits notably high Zin. The minimum attainable supply voltage for the recommended amplifier is primarily constrained by the elevated threshold voltages inherent in the transistors utilized within the 180 nm CMOS technology, aligning with trends observed in comparable amplifiers presented. Furthermore, the power dissipation is relatively significant, reaching a maximum value of 29.61 μW.
Monte Carlo simulations offer a statistical examination of amplifier performance in the presence of process fluctuations, enabling designers to evaluate the efficacy of adaptive approaches in mitigating the standard deviation of performance measurements. This evaluation involved the utilization of 200 Monte Carlo simulations, which considered the effects of mismatches and various factors. The histogram representing the differential gain, common mode gain, and CMRR may be observed in Figs 14–17. The bio-potential amplifier exhibits minor variations for the majority of these parameters. For instance, the mean values of the differential gain, CMRR, common mode gain, and offset voltage are 65.009 dB, 97.76 dB, -33.65, and 925.615 nv respectively, and the standard deviations are 1.83, 9.88, 9.31, and 116.308 nV, respectively. The observed decrease in standard deviation suggests that the amplifier design exhibits enhanced robustness and durability when employed in real-world scenarios. Evaluation of the robustness and reliability of an amplifier design considers not only the reduction in standard deviation but also other key performance metrics. Furthermore, it showcases their ability to maintain consistent performance benchmarks amidst diverse and challenging conditions, encompassing fluctuations in processes, temperature shifts, and fluctuations in supply voltage.
The results of the voltage and temperature variation analysis are illustrated in Fig 18. A comprehensive investigation of the circuit’s performance under challenging conditions of Corner fluctuations and temperature changes was conducted. To ensure precision across various temperature ranges (0°C, 27°C, 75°C) and corner limits (FF FS SF SS), the system underwent thorough scrutiny for fluctuations in both gain and CMRR, all kept within a 10% margin. This scrutiny serves as compelling evidence of the system’s accuracy and performance. The presented evidence is crucial in validating the efficacy of adaptive amplifier designs in real-world scenarios, as it showcases their capacity to achieve the intended performance even in the most unfavorable conditions.
Conclusion
This work presents a high-performance switched capacitor chopper amplifier based on the FVF adaptive biasing technique and SCCMs-based active load. This modified amplifier is an excellent alternative where the input signal is significantly weaker than the common mode signal, such as those found in bio-potential amplifiers. The suggested chopper amplifier design demonstrates a notable improvement in gain and CMRR, which are 63.72 dB and 127.97 dB, respectively. The utilization of the suggested amplifier increases the input impedance while simultaneously achieving low noise and low power consumption. The simulation results of the suggested amplifier are analyzed using the Cadence Virtuoso tool, employing a 180 nm CMOS technology node and a supply voltage of 0.8 V. These findings are subsequently compared to pertinent results in the current literature and validated through Monte Carlo simulations exhibiting reduced standard deviation. Ultimately, it has been shown that the CMRR can be improved by introducing capacitive load in alternative SC amplifiers, provided that it does not impact the differential gain. Overall, the suggested work provides an enabling technology for biological applications.
A Appendix
By applying the superposition theorem to the loop circuit of Fig 1 at node “p” loop equation is
(9)
In the same way node “n” loop equation is
(12)
The differential amplifier input-output relationship is
(13)
(14)
The closed-loop gain transfer function across the amplifier without chopper modulators is
(15)
B Appendix
The OTA analysis
(17)
(18)
(19)
(20)
Apply KCL at different nodes in FVF-OTA
(21)
(22)
(23)
(24)
(25)
(26)
From (17) and (23); (assume RB ≫ 1), can be simplified as
Similarly, from (18) and (24) (assume RB ≫ 1), can be simplified as
(27)
(28)
From Eq (27), (assume and
), the value of voltage Ion can be written as
From Eq (28), (assume and
), the output current Iop can be written as
the output current Io can be written as
(29)
Using Eqs (21) and (22) (assuming and
),
Value of and
can be obtained from Eqs (19) and (20). Therefore, Gm can be obtained as
(31)
The output resistance (rO) of OTA is given as
(32)
Acknowledgments
We sincerely thank VIT-AP University for providing resources and facilities for the smooth functioning of the research work.
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