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Open Access

Correction

Correction: Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP

  • Agustín Navarro-Torres,
  • Jesús Alastruey-Benedé,
  • Pablo Ibáñez-Marín,
  • Víctor Viñals-Yúfera

The Data Availability statement for this paper is incorrect. The correct statement is: All data are available at https://github.com/agusnt/Xeon-SP_Memory_Characterization_SPEC-CPU-2K6-2K17/.

Reference

  1. 1. Navarro-Torres A, Alastruey-Benedé J, Ibáñez-Marín P, Viñals-Yúfera V (2019) Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP. PLoS ONE 14(8): e0220135. pmid:31369592

Citation: Navarro-Torres A, Alastruey-Benedé J, Ibáñez-Marín P, Viñals-Yúfera V (2024) Correction: Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP. PLoS ONE 19(5): e0303712. https://doi.org/10.1371/journal.pone.0303712

Published: May 9, 2024

Copyright: © 2024 Navarro-Torres et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.