Introduction

Titanium nitride (TiN) is a potential application specific material, which provides a favourable combination of physical and chemical properties for semiconductor manufacturing such as low resistance, comparatively high transmittance within the visible spectrum, hardness and chemical resistance [1]. Titanium nitride also possesses good quality mechanical, tribological, electrical, biomedical, and optical properties. The reliance of the mechanical and electrical properties of titanium nitride thin films deposited with the help of variety of techniques upon silicon substrates have been studied in past to exhibit their potential for CMOS industry driven applications [2]. In some previous studies [3–4], the TiN-Si hetrojunctions were fabricated by the deposition of TiN thin films onto the refined Si substrates by using the DC reactive magnetron sputtering. These nitrides have also shown to exhibit the property to tune the work function due to their thermal stability [5]. Currently, research on various electrode materials, starting from polycrystalline metal films to composite conducting oxides, is being carried out [5]. With TiN placed effectively as ultra-thin layer or part of the compositional stack in Si CMOS processing. The thermal stability and electrical properties of one such stack in metal oxide semiconductor (MOS) capacitors after post-metal annealing in H₂ or N₂+H₂ ambient in a range of temperature 30 minutes are examined [6] and analyzed. C-V profiling for characterization of these nano-scale devices has been a standard analytical technique in manufacturing industry [7]. NMOS C-V profiling techniques (the conventional Capacitance-Voltage profiling and deep depletion (DD) C-V have also been in practice to profile the subject devices [8]. Similarly, optical characterization of titanium nitride is accomplished by means of ellipsometry, and electrical characterization is performed using C-V and I-V profiling to obtain the work function and resistivity of these thin sensitive films [6].

In this paper, we investigate the MOSCAP structure as part of the CMOS family in terms of its sensitive electrical characteristics including detailed I-V and C-V analysis. The study is targeted towards TiN ultra-thin film as the gate electrode in the MOSCAP structure. As a substitute to the conventional gate dielectric (SiO₂), high-k HfSiO is used as dielectric material beneath the gate metal for the device structure as shown in Fig 1. Hafnium Silicate has proven to be a promising dielectric material with low diffusivity of impurities and channel mobility features.

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Fig 1. MOSCAP Structure used in this work (Device Cross Section).

https://doi.org/10.1371/journal.pone.0161736.g001

Experimental

MOSCAP structure is fabricated by utilizing HfSiO layer as high-k dielectric material instead of conventional SiO₂ knowing its competitiveness of EOT scaling. Atomic layer deposition (ALD) technique is used for the deposition of both the high-k dielectric HfSiO layer and TiN metal gate in NLD-4000 ALD system. The deposition chamber is preheated at 315°C and the substrate of Si (100) is placed in the reaction chamber. A high -k dielectric layer is deposited by injecting the Hf and Si liquid precursors one by one resulting into a proper reaction yielding a fine layer of dielectric material. Following this, TiN layer is deposited on top of the dielectric layer onto the same wafer using the same ALD technique. The chamber temperature is maintained at 400°C with TiCl₄ and NH₃ gases duly injected in the reaction chamber for TiN ultra-thin deposition. TiCl₄ is injected with N₂ which is used as a carrier gas (also acted as a purge gas) at the same time. High purity ammonia gas (~99%) is used as a reactant. The working pressure of the reaction chamber was maintained at 0.55 Torr (with ±5% of control accuracy). Detailed ALD process parameters to deposit these ultra- thin layers on Si (100) standard wafer are summarized in Table 1.

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Table 1. Atomic Layer Deposition Process Conditions for HfSiO and TiN Ultra-Thin Layers to fabricate the device structure.

https://doi.org/10.1371/journal.pone.0161736.t001

All the annealing schedules are performed on the Rapid Thermal Processor (RTP) during the processing of MOSCAP structures. Rapid Thermal Processor (RTP) is known to reduce the thermal redistribution of impurities at relatively high temperature. The exposure of the samples to the heating flow for relatively smaller times also tends to reduce the probabilities of oxidation of TiN films. Post deposition annealing of HfSiO is carried out in RTP for 470°C with no ramps of temperature in between and dwelled at 30 seconds. The ambience of nitrogen is chosen to purge the environment with a cooling effect. The atomic layer deposited TiN ultra-thin layer is also subjected to RTP with temperatures intentionally chosen to be in the process window from 600°C to 1000°C for 20 seconds in each case. Again, a nitrogen gas ambience is created to anneal the samples at nominal atmospheric pressure. The electrical characteristics of the MOSCAP devices are measured using a sophisticated Automatic System for Material Electro-Physical Characterization (ASMEC) tool in the Advanced Electronics Laboratory.

Results and Discussion

I-V Characteristics and Leakage Resistance

Fig 2 shows the I-V profiles of the MOSCAP structure with HfSiO as dielectric material TiN and ultra-thin film as gate electrode, and subjected to relatively medium to slightly higher annealing temperatures. Fig 2, when closely examined, reveals that the leakage current is reduced with the increasing post-process annealing cycle until 900°C. A slight increase is noticed when the annealing temperature goes to 1000°C. This in turn shows an increase of leakage resistance with the increasing annealing temperatures. At relatively higher annealing temperatures (900–1000°C of process window); the change in the leakage resistance is almost negligible. The current profile, as depicted in Fig 2 is at maximum for the sample annealed at a temperature of 600°C. The obtained curves follow the pattern as in [9–10], which is a similar study for I-V curves for evaluating the metal gate electrode behavior. Our results are consistent with those obtained in [11–12] since the rise of temperature does not necessarily transform into enhanced conductivity; this phenomenon can be attributed to metal gate and dielectric interface defect states [13]. We also observe from our results that the rise of the annealing temperature also improves the linearity of the I-V correlation i.e. the linearity is much pronounced for the devices undergone the annealing temperatures of 800°C, 900°C and 1000°C in comparison to the ones with 600°C and 700°C. The possible presence of defects in the structure and randomness of the defect (vacancies in particular) interaction with the device matrix and their annihilation is thought to be responsible for the non-linearity and its gradual recovery in the signature I-V curves for various annealing conditions (Fig 2b–2f). Fig 2 also depicts that the MOSCAP structure having TiN thin layers deposited by ALD and undergone a rapid thermal process cycle at 600°C for 20 seconds does not maintain the leakage current against all bias values. For example, low voltages yield an appreciable leakage current. In other words; leakage resistance is maximum at low voltages for sample annealed at 600°C. As the voltage increases, the resistance shows a constant behavior. This provides a flexible process window to attain device output parameters at desirable bias condition.

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Fig 2. Leakage Resistance and I-V characteristics for different annealing temperatures.

(a) Leakage Resistance at different annealing temperatures. (b) I-V characteristic curve for 600°C. (c) I-V characteristic curve for 700°C. (d) I-V characteristic curve for 800°C. (e) I-V characteristic curve for 900°C. (f) I-V characteristic curve for 1000°C.

https://doi.org/10.1371/journal.pone.0161736.g002

C-V Profiling

An analysis is made for the electrical characteristics of MOSCAP with TiN gate electrode at various annealing temperatures. The Capacitance-Voltage profiling is done with the help of ASMEC equipment, which is used for the electrical characterization for parameters such as I-V, C-V, QDLTS etc. The C-V profiles obtained for MOSCAP devices undergoes different annealing cycles between 600°C and 1000°C are shown in Fig 3. The C-V curves shown in Fig 3 are in close approximation with the standard curve for MOSCAP found in the literature [7]. It is evident that the values of capacitances change with the variation of the annealing cycles subjected to the MOSCAP device structure. The devices, which have undergone the rapid thermal processing of 600°C and 700°C, reflect a positive threshold voltage as compared to the ones with negative voltage for higher annealing temperatures. The threshold voltage becomes more negative as soon as the temperature rises beyond 900°C. This signifies that the slope of the representing curves (depletion in physical terms) decreases with the increase of the annealing temperatures. It is also exhibited that the samples annealed at 800°C have the lowest value of capacitance i.e. 65 pF at a voltage of about 0.5 V. The lower value of capacitance translates into lower electrostatic losses and consequently lower leakages. As the C-V profiling executed for these MOSCAP devices is performed at an operating frequency of 1.2 kHz, this may provide an estimate of the possible presence of different kinds of defects and interstitial states present in the structure. The trends are somewhat similar to an earlier study carried out at low frequencies [12]. The increase in capacitance especially at low frequency is likely to be attributed to the presence of interstitial state at Si/SiO₂ interface in conventional MOSCAP structures [13]. The dangling bonds, humps, stretch out oxygen vacancies during deposition are also reported to play a significant role in the shift of flat band voltage for such devices [14]. The post process annealing has known influence on the dynamic re-structuring of defects and is reported to improve the mobility and threshold slopes for equivalent devices [14], such as in our case.

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Fig 3. C-V Hysteresis for samples at different annealing Temperatures.

(a) C-V profiles at different annealing ranging from 600 to 1000°C. (b) C-V profiling for 600°C. (c) C-V profiling for 700°C. (d) C-V profiling for 800°C. (e) C-V profiling for 900°C. (f) C-V profiling for 1000°C.

https://doi.org/10.1371/journal.pone.0161736.g003

Doping Profile and Built in Potential

Fig 4 explains a correlation between the post-process annealing temperature with the effective doping profile (N_d-N_a) and the built-in potential for MOSCAP with ultra-thin TiN metal gate structured with ALD. The doping profile N_d-N_a is visible to be highest for samples annealed at 900°C. The built in voltage V_b is also the highest for the 900°C annealed samples owing to the higher annealing temperature drawing out relatively larger number of majority carriers from the lattice.

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Fig 4. Doping profile and Built in voltage as a function of Annealing Temperature.

https://doi.org/10.1371/journal.pone.0161736.g004

The built in voltage depends directly on the number of dopants in such a way that higher number of dopant atoms yield a concentrated doping profile and a wider depletion region. Consequently, the higher built in voltage is achieved. The higher annealing temperature, as expected, results in fewer interfaces state densities and hence the probability of having defects decreases in the interface state and consequently lesser energy is required to vacate any carrier implying energy efficiency [9].

Conclusion

We fabricated specifically designed MOSCAP structures, for possible integration with CMOS technology, with atomic layer deposited HfSiO and TiN thin layers as high-k dielectric and metal gate, respectively. The devices were subjected to post deposition and post-metal annealing cycles with carefully chosen rapid thermal process parameters. Low frequency electrical characterization was performed in order to tune the trade-off between the C-V hysteresis and the leakage current at the gate to facilitate design an effective energy efficient CMOS nano-electronics. It is found that the profiles obtained after different annealing temperatures are shown to closely follow the standard C-V curve for MOSCAP at low frequencies. The largest value (voltage) of the knee of the curve signifying transition from accumulation to depletion is for a sample annealed at 600°C. The slope (depletion) of the electrical profile of the device structure is found to decrease with the increasing rapid thermal annealing temperature. The leakage resistance reflects a maximum value at low voltages with almost a constant behavior with increasing bias. The threshold voltages are proving to be more negative at relatively higher annealing temperatures. The optimized device output characteristic window provides a trade-off between the desirable electrical entities such as C-V hysteresis, leakage current, flat-band voltage and leakage resistance, with the control of process conditions during the annealing kinetics. This may prove to be a way forward to design energy efficient CMOS electronics at desirable bias.

Supporting Information