Fig 1.
Functions and approaches included in the modeling method.
Fig 2.
Cross-section schematic of the four-layer PCB structure.
Fig 3.
Schematic of a PCB under Cartesian coordinates.
Fig 4.
Diagram of the discrete cells along the lateral sides of the PCB.
Fig 5.
Schematic diagram of heat conduction through discrete cells in the metal layer.
Fig 6.
Program flow chart of the test solver.
(a) Model construction program. (b) Model calculation program.
Fig 7.
Metal layer layouts of Structure A.
(a) first layer. (b) second layer. (c) third layer. (d) fourth layer.
Table 1.
Modeling condition definition related to the model of Structure A.
Fig 8.
Schematic diagram of discrete cells under a three-level multigrid.
Fig 9.
Mesh and simulation parameters of the COMSOL model of Structure A with Thcore = 0.15 mm under Case-2.
(a) Mesh view. (b) Mesh quality under “Fine” level. (c) Simulation parameters.
Fig 10.
Temperature maps of the first-layer surface of Structure A with Thcore = 0.15 mm.
(a) Case-1. (b) Case-2. (c) Figure with COMSOL data. (d) COMSOL output. (e) COMSOL convergence curve of the hotspot temperature under Case-2. (f) Temperature profiles along the marking line.
Fig 11.
Temperature maps of the first-layer surface of Structure A with Thcore = 0.55 mm.
(a) Case-1. (b) Case-2. (c) Figure with COMSOL data. (d) COMSOL output. (e) COMSOL convergence curve of the hotspot temperature under Case-2. (f) Temperature profiles along the marking line.
Fig 12.
Comparison of temperature curves of the marking hot region between Case-2 and COMSOL models with different Pd.
(a) Thcore = 0.15 mm. (b) Thcore = 0.55 mm.
Fig 13.
Comparison of temperature maps of other three layer surfaces between Case-2 (top figures) and COMSOL (middle: figures with COMSOL data, and bottom: COMSOL output) models with Thcore = 0.15 mm and Pd = 1W.
Fig 14.
Circuit schematic of the PCB.
Fig 15.
(a) first layer. (b) second layer. (c) third layer. (d) fourth layer. (e) top surface photo of the PCB.
Table 2.
Components’ type, RθJB and RθJC(top), as well as Area (AR) and Radiation Emissivity(ℇ) Considered for Radiation.
Fig 16.
Layout maps of the PCB used for modeling: (a) first layer.
(b) second layer. (c) third layer. (d) fourth layer. (e) soldering pads. (f) components’ area. (g) coverage region of the nylon stick.
Fig 17.
Experimental setup showing the thermal camera and board.
Fig 18.
Thermal image of the PCB with Load A.
Fig 19.
Simulated temperature maps of each layer surface of the PCB with Load A.
(a) the first-layer surface. (b) the second-layer surface. (c) the third-layer surface. (d) the fourth-layer surface.
Fig 20.
Thermal image of the PCB with Load B.
Fig 21.
Simulated temperature maps of each layer surface of the PCB with Load B.
(a) the first-layer surface. (b) the second-layer surface. (c) the third-layer surface. (d) the fourth-layer surface.
Fig 22.
Simulated electric-potential maps of the main-circuit traces of the PCB with Load B.
(a) Vin (V) trace of the top layer. (b) Vout (V) trace of the top layer. (c) VGND (10-4V) trace of the top layer. (d) VGND (10-4V) trace of the 2nd layer. (e) Vin (V) trace of the 3rd layer. (f) Vout (V) trace of the 3rd layer. (g) VGND (10-4V) trace of the 4th layer.
Fig 23.
New layout maps of the PCB.
Fig 24.
Simulated electric-potential (V) maps of the Vout traces of the new layout of the PCB with Load B.
(a) the top layer. (b) the 3rd layer.
Fig 25.
Simulated temperature map of the top layer surface of the new layout of the PCB with Load B.