Fig 1.
Overall structure of memory system interface.
Fig 2.
Architecture of memory address generation module.
Table 1.
Addressing table for registers within address generation module.
Fig 3.
Structure of the memory data input channel.
Fig 4.
Schematic structure of optoelectronic signal.
Fig 5.
Principle of TTBC (one bit).
Table 2.
Resistance values and ranges of G, R1 and R2 (Unit: MΩ).
Fig 6.
Principle of binary signal transmitter.
Fig 7.
Structure of the memory data output channel.
Fig 8.
Schematic diagram of optical signal generator.
Fig 9.
Memory interface read/write timing diagram.
Fig 10.
Working process of input channel.
Fig 11.
State transition diagram of experimental design.
Fig 12.
FPGA experimental simulation results.
Table 3.
10 groups of experimental test cases.