Fig 1.
Block diagram of HEVC Encoding process.
Fig 2.
Flowchart for Algorithm 1 depicting serial FS ME process.
Fig 3.
Block diagram for Algorithm 2, explaining the parallelization provided by the GPU threads for FS ME process.
Fig 4.
Block diagram for Algorithm 3, explaining the parallelization provided by the GPU threads for FS ME process.
Macroblock level parallelization has been depicted.
Fig 5.
Block diagram for Algorithm 4, explaining the parallelization provided by the GPU threads for FS ME process.
SA level and Macroblock level parallelization has been depicted.
Fig 6.
Block diagram for Algorithm 5, explaining the parallelization provided by the GPU threads for FS ME process.
Frame level and macroblock level parallelization has been depicted.
Fig 7.
Block diagram for Algorithm 7, explaining the parallelization provided by the GPU threads for FS ME process.
SAD level parallelization has been depicted.
Fig 8.
Block diagram for Algorithm 9, explaining the parallelization provided by the GPU threads for EHDS ME process.
Creation of hierarchy of multiple resolution images.
Fig 9.
Block diagram for Algorithm 11, explaining the parallelization provided by the GPU threads for EHDS ME process.
Macroblock level and SAD level parallelization is depicted.
Fig 10.
Block diagram for Algorithm 13, explaining the parallelization achieved using GPU threads, for motion compensation process.
Fig 11.
Block diagram for Algorithm 15, explaining the parallelization achieved using GPU threads, for image differencing process.
Fig 12.
Block diagram for Algorithm 19, explaining the parallelization achieved using GPU threads, for conventional 2D DCT process.
Fig 13.
Block diagram of 8-point Loeffler 1D-DCT Algorithm.
Fig 14.
Symbols used for the Loeffler DCT algorithm.
Fig 15.
Block diagram for overall ME, motion compensation, image differencing and 2D DCT processes explaining the parallelization achieved using GPU threads.
Table 1.
Time consumption of the implementations.
Table 2.
Comparison with the state of the art for ME.