Fig 1.
Proposed Full-bridge resonant cascaded (FBRC) step-up dc-dc converter.
Fig 2.
Key waveforms of the developed FBRC converter.
Fig 3.
Current flow routes of the developed FBRC converter.
(a) Operating Mode I. (b) Mode II-a. (c) Mode II-b.
Fig 4.
Current flow routes of the developed FBRC converter.
(a)Mode III. (b)Mode IV-a. (c) Mode IV-b.
Fig 5.
Voltage gain and duty cycle comparison.
Fig 6.
Comparison of voltage gain and number of major components.
Fig 7.
Input current ripple versus input inductance.
Table 1.
Comparison among conventional high voltage step-up ratio converters with the suggested converter.
Fig 8.
Comparison of the voltage stresses on the capacitor of the proposed and other converters.
Fig 9.
Capacitor voltage and output voltage ripple.
Fig 10.
Voltage unbalanced ripple on the capacitor.
Fig 11.
Voltage stress on switch of the proposed FBRC converter.
Table 2.
Comparison among the output power, duty cycle, voltage gain, voltage and current ripples, and efficiency of different dc-dc converters.
Fig 12.
(a) Full-bridge module. (b) Control gate signals of the full-bridge module of the proposed converter.
Table 3.
The proposed converter prototype’s specifications.
Table 4.
Description of suggested converter prototype’s components.
Fig 13.
Block diagram of the control technique of the proposed converter.
Fig 14.
FBRC converter hardware implementation.
Fig 15.
Simulation waves of Vb and ir, output voltage and current, Vo and Io, and input current iLs.
Fig 16.
Experimental switching signals of the four FB MOSFET gates.
Fig 17.
Experimental results of FB voltage (vb) and resonant current (ir).
Fig 18.
ZVS turn-off and turn-on with voltage spike at fSL(88kHz) > fr(80kHz) of the switch SL1.
Fig 19.
Turn-off and turn-on with hard switching at fSL(38 kHz) < fr/2 of the switch SL1.
Fig 20.
Turn-off and turn-on with hard switching at fr/2 < fSL(50 kHz) < fr of the switch SL1.
Fig 21.
Voltage gain versus frequency ratio.
Fig 22.
ZVS turn-off and turn-on operation at 25% load of SL1.
Fig 23.
ZVS turn-off and turn-on operation at 100% load of SL1.
Fig 24.
ZVS turn-off and turn-on operation at 25% load of SU1.
Fig 25.
ZVS turn-off and turn-on operation at 100% load of SU1.
Fig 26.
Experimental dynamic response of the PID controller due to load changes.
(a) Load increased from 50% to 100%. (b) Load decreased from 100% to 50%.
Fig 27.
Experimental dynamic responses of the PID controller due to input voltage variations.
(a) Input voltage increased from 60V to 70V. (b) Input voltage decreased from 60V to 50V.
Fig 28.
Experimental output voltage, input boost inductor current, and output current.
Fig 29.
Estimated power losses of different main components used in this converter.
Fig 30.
Converter measured efficiency at various loads.
Fig 31.
Measured efficiency vs duty cycle.