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Fig 1.

Existing H-bridge derived CGT boost Inverters: (a) structure presented in [10], (b) structure presented in [11,12], (c) structure presented.

in [13], and (d) structure presented in [14].

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Fig 1 Expand

Fig 2.

The proposed three-level common ground type inverter topology.

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Fig 2 Expand

Fig 3.

Modes of operation of the proposed type topology: (a) mode 1, (b) mode 2, (c) mode 3, (d) mode 4 and (e) mode 5.

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Fig 3 Expand

Table 1.

Switching sequence of the proposed boost inverter.

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Table 1 Expand

Fig 4.

Typical two-level output voltage waveform and gate pulses.

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Fig 4 Expand

Fig 5.

PLECS power loss calculation: (a) total cycle average losses calculation method and (b) power loss breakdown for the different components.

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Fig 5 Expand

Table 2.

Component comparison between the proposed topology and different existing topologies*.

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Table 2 Expand

Fig 6.

Extended structure of two DC sources with common ground.

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Fig 6 Expand

Fig 7.

Simulation results: (a) inverter output voltage (vinv), (b) grid voltage (vg) and current (ig), (c) capacitor voltage (vC1), (d) capacitor voltage (vC2), (e) inductor voltage (vL), and (f) inductor current (iL).

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Fig 7 Expand

Fig 8.

Hardware setup of the proposed topology.

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Fig 8 Expand

Fig 9.

Experimental result: (a) vo and io at (R=50 Ω, L=50 mH), (b) vo and io at (R=50 Ω, L=50 mH) to (50 Ω+100 mH), and (c) vC1, vL, vC2, and iL for (R=50 Ω, L=50 mH).

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Fig 9 Expand

Fig 10.

Experimental results in case of changing the input voltage from 75 V to 100 V: (a) vo and io, (b) vC1, vL, vC2, and iL and (c) output voltage and current at a modulation index of 0.5.

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Fig 10 Expand

Fig 11.

Control scheme for grid-tied PV system with the proposed inverter.

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Fig 11 Expand

Fig 12.

LCL filter design: (a) circuit diagram and (b) bode plot.

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Fig 12 Expand

Table 3.

LCL Filter design value.

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Table 3 Expand

Fig 13.

Experimental result of vo, vg, and ig after LCL filter placement with load variation.

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Fig 13 Expand

Fig 14.

Experimental results of closed-loop (a) at unity PF, (b) at 0.71 lagging PF, (c) at 0.71 leading PF, and (d) during change of reference current (ig, ref) from 1.5 A to 3 A.

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Fig 14 Expand

Table 4.

Cost comparison of the proposed topology with the existing topologies for vo=200 v.

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Table 4 Expand

Fig 15.

Efficiency variation for various power levels.

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Fig 15 Expand

Fig 16.

FFT analysis (a) Voltage THD (VTHD), (b) Current THD (ITHD).

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Fig 16 Expand