Fig 1.
Relation between four fundamental circuit elements: Resistor, capacitor, inductor and memristor.
Fig 2.
Biasing of memristor (inset—Memristor symbol).
Table 1.
Numerical values of parameters used in the model.
Fig 3.
MRL Inverter.
Fig 4.
D-Latch with MRL inverters and memristor.
Fig 5.
Functional flow of non-volatile D-Latch.
Fig 6.
(a) Simulated waveform of MRL based non-volatile D-Latch. (b)Propagation delay in MRL based non-volatile D-Latch.
Table 2.
Truth table of D-Latch.
Fig 7.
Master-slave D-flip-flop with MRL inverters and memristor.
Fig 8.
Simulated waveform of master-slave D flip-flop.
Fig 9.
Mod-4 counter.
Fig 10.
A four-bit SISO shift register.
Fig 11.
Simulated waveform Mod-4 counter.
Fig 12.
Simulated waveform of four-bit SISO register.
Fig 13.
MRL inverter based traditional CMOS flip-flop.
Fig 14.
Simulated waveform of MRL inverter based traditional CMOS flip-flop.
Table 3.
Comparison of non-volatile memristor based D-Latch.
Table 4.
Comparison of non-volatile memristor based master-slave flip-flop.