Fig 1.
(a) Block diagram of an IO-mode asynchronous circuit stage. Example completion detect circuits corresponding to (b) RZH, (c) ROH, and input registers.
Fig 2.
Dual-rail encoded asynchronous N-bit RCA comprising N full adders.
Fig 3.
(a) N-bit standard CLA (SCLA), and (b) N-bit block CLA (BCLA). In the figure, N-bit SCLA and BCLA are constructed by replicating and cascading 4-bit SCLA and BCLA modules respectively for an example.
Fig 4.
Example illustration of an N-bit BCLA comprising double carry logic (BCLADC).
Fig 5.
Building blocks of proposed monotonic asynchronous SCLA based on dual-rail encoding, corresponding to RZH: (a) generic realization of carry propagate, generate, and kill functions; (b)–(e) example implementation of 4-bit look-ahead carry outputs (C41, C40) up to (C11, C10); and (f) generic realization of sum output.
Fig 6.
Building blocks of proposed monotonic asynchronous BCLA employing dual-rail encoding and corresponding to RZH: (a) generic realization of carry propagate, generate and kill functions; (b) example 4-bit BCLG implementation; (c) monotonic full adder; and (d) monotonic 3-input XOR function.
Table 1.
Cycle time (theoretical) of N-bit IO-mode asynchronous adders.
N-bit RCAs were constructed using N full adders. N-bit CLAs were constructed using M-bit CLA modules where N and M are even and N modulo M equals 0; here M = 4.
Table 2.
Design metrics of different 32-bit asynchronous adders corresponding to RZH, implemented using a 28-nm CMOS process.
Table 3.
Design metrics of different 32-bit asynchronous adders corresponding to ROH, implemented using a 28-nm CMOS process.
Fig 7.
Normalized power-cycle time product (PCTP) of 32-bit asynchronous adders corresponding to (a) return-to-zero handshaking, and (b) return-to-one handshaking. Adder legends used in (a) and (b) are referred to in Tables 2 and 3 respectively. The normalized PCTP values of proposed CLAs are highlighted by the red bars in (a) and (b).