Fig 1.
(a) the top view of the proposed VPISDC-HSB-BTFET, (b) the cross views along cut line A in (a), (c) the cross views along cut line B in (a).
Fig 2.
(a) the top view of the proposed VPISDC-HSB-BTFET, (b) the cross views along cut line A in (a), (c) the cross views along cut line B in (a).
Fig 3.
(a) Calibration between a simulated SB-MOSFET and an experimental SB-MOSFET. (b) Transfer characteristics comparison between HSB-BTFET and VPISDC-HSB-BTFET. (b) The IDS-VGS characteristic curve of different vertical channel heights.
Fig 4.
The total current density distribution and the electron concentration in the horizontal silicon body channel under the control of assistant gate in on state between (a) the proposed VPISDC-HSB-BRFET with 1000nm HV, (b) the proposed VPISDC-HSB-BRFET with 50nm HV and (c) the previously proposed HSB-BRFET.
Fig 5.
The total current density distribution in the vertical channel under the control of main gate in on state between (a) the proposed VPISDC-HSB-BRFET with 1000nm HV and (b) the proposed VPISDC-HSB-BRFET with 50nm HV.
Fig 6.
The comparison of transfer characteristics of the VPISDC-HSB-BTFET with different horizontal channel heights.
Fig 7.
The comparison of transfer characteristics of the VPISDC-HSB-BTFET with different assistant gate voltages.
Fig 8.
Output characteristics of the proposed VPISDC-HSB-BTFET with different VGSs.
Fig 9.
(a) Top view of the conventional FinFET, (b) cross views along cut line A in (a), (c) cross views along cut line B in (a).
Fig 10.
Transfer characteristics comparison between VPISDC-HSB-BTFET and FinFET.
Table 1.
Comparison of Ion/Ioff ratio between highly sensitive devices and the mainstream FinFET technology.
Fig 11.