Fig 1.
Schematic diagrams of AlSi3 FET: (a) the structure and (b) the ToB nanotransistor circuit model. The gate, drain and source terminal capacitances are denoted as CG, CD, and CS, respectively.
Fig 2.
Overall flowchart of this study.
Table 1.
The device parameters of AlSi3 FETs.
Fig 3.
I-V characteristics of AlSi3 FET simulated using (a) ToB nanotransistor model and (b) SPICE model.
Fig 4.
Comparison between the ToB nanotransistor model and SPICE model of the AlSi3 FET.
The empty dots in (a) represent the results of the ToB nanotransistor model while the solid lines in (a) represent the results of the SPICE model.
Fig 5.
Definitions of the device performance metrics of a FET.
Fig 6.
Device performances analysis between the proposed AlSi3 FET model with published transistor models based on various low-dimensional materials.
NA (not available) in the bar graphs denotes the unavailable data.