Fig 1.
AES encryption and decryption.
Fig 2.
AES BIST architecture.
Fig 3.
Functional blocks of the AES Crypto ASIC with BIST.
Fig 4.
Flowchart of the AES Crypto ASIC with BIST.
Table 1.
Used resources in FPGA simulation.
Fig 5.
Simulation result of encryption module in normal mode.
Fig 6.
Simulation result of decryption module in normal mode.
Fig 7.
Simulation result of decryption process following encryption process.
Fig 8.
Simulation result of encryption module in test mode.
Fig 9.
Simulation result of decryption module in test mode.
Table 2.
Comparison results of the AES in terms of BIST implementation.