Fig 1.
The general shape of the time-dependent logistic model compared with the curve following semilog transformation.
A) The logistic model on a linear scale. B) The semilog transformation of the logistic model. Note the nearly exponential behavior of the initial phase of the function. The midpoint half-saturation point (τ) and asymptotic saturation (K) are shown.
Fig 2.
A power-law relationship between state-of-the-art processor size and the number of transistors (T∝A4.4, P< 0.001).
Fig 3.
State-of-the-art integrated circuit density (transistors∙mm-2) per year.
The two exponential growth phases are characterized by doubling times of 17 and 33 months, respectively. Data are heteroscedastic and autocorrelated, consistently underestimating all data since 1999.
Table 1.
Stepwise exponential model parameter values.
Fig 4.
The temporal trend of transistor density.
A) The data exhibit a bi-logistic curve. B) Decomposition and linearization of the individual trends are depicted as percent of growth for each of the two phases. Parameter values are shown in Table 2.
Table 2.
Bi-logistic parameter values.
Fig 5.
Approximated second derivative exhibits complex acceleration and deceleration patterns in the data.
Arrows indicate inflection points where growth rates decline.
Fig 6.
Decomposition and linearization of data into corresponding individual loglet trends highlighting distinct phases of transistor evolution.
See Table 3 for fitted model parameter values.
Table 3.
Bi-logistic parameter values.
Fig 7.
Decreasing mean transistor size since 2000.
Fig 8.
A “hyperlogistic” function fitted to the inflection points of the six identified logistic wavelets.