Fig 1.
The direction of the score computation in the matrix during the SW forward stage.
To determine a score, such as w, the neighborhood values (x, y, and v) have to be known. The green-colored cells indicate already computed values, while the yellow cells indicate that the values to be calculated.
Fig 2.
General architecture for the SW algorithm.
The forward stage (MSM) is represented by the blue block, the backtracking stage (BS) by the yellow block, and the Memory (MM) by the green block. Only external signals are displayed, i.e., the q and s signals.
Fig 3.
Architecture of each PE in the systolic array.
The forward stage is represented by the blue block, the backtracking stage by the yellow block, and the Memory by the green block.
Table 1.
Description of signals and the algorithm stage they are used.
The forward stage is represented by F, storage stage by F, and backtracking stage by B. They are shown in the Figs 4, 7 and 8.
Fig 4.
Hardware representation of the H score matrix on the forward stage.
The modules are generated from 0 to N − 1.
Fig 5.
Submodules that constitute a Matrix Score Module.
The representation of the circuit and signals is only related to the forward stage.
Fig 6.
Circuits that constitute the submodule for finding the maximum score and distance path within an MSM.
The relational circuits are represented in purple and the multiplexers in yellow.
Fig 7.
Representation of the simplified Memory Module structure.
This model is practically as is the complete processing PE of each column of the H matrix.
Fig 8.
Backtracking Module structure in the FPGA.
The operation of this block starts after the forward step.
Fig 9.
Submodules that constitute the backtracking stage module.
The green submodules represent the control submodules, while the blue submodule represents the circuit that performs the alignment.
Fig 10.
Logical circuits used to build the Alignment Block submodule.
Fig 11.
Photo of the hardware architecture deployed on the Virtex-6 FPGA and the host computer used to plot the results.
Fig 12.
Illustration of the results obtained from our proposal in co-simulation.
The image is the most detailed representation of the monitor in Fig 11. It can see that the y-axis refers to the s, while the x-axis refers to the q. The position at which the alignment starts is indicated by Row and Column. The maximum score value found is presented by Maximum Value. The amount of sequence alignment performed is represented by Number of Alignments.
Table 2.
Area occupation results based on the FPGA synthesis of our SW implementation, with forward and backtracking stages.
Table 3.
Table adapted from paper [23].
Table 4.
Table with the summaries of the results of the FPGA synthesis works of SW implementation (hardware SW with backtracking step).
The Slice column is related to the logical distribution and refers to the occupied slices in the synthesis.