Fig 1.
Schematic structure and circuit diagrams of n-type and p-type uniformly doped silicene FETs.
Brown atoms represent silicon (Si) atoms; purple atoms represent aluminium (Al) atoms; and grey atoms represent phosphorus (P) atoms.
Fig 2.
Modelling and simulation flow chart of this work.
Table 1.
Electronic properties of uniformly doped silicene nanosheets.
Fig 3.
The non-linear regression fit for self-consistent potential: (a) p-type AlSi3 and (b) n-type PSi3. The dots are USCF data from ToB model; and the coloured plane is the plot of fifth order polynomial equation.
Table 2.
Comparison of Ion/Ioff ratio of the proposed model with published 2D material-based FET models.
Fig 4.
Comparison of I-V characteristics between iterative and non-iterative TOB nanotransistor models.
Fig 5.
Schematic circuit diagram of silicene-based inverter (Lint = 1 μm) with its input (blue) and corresponding output waveforms (red).
Fig 6.
Schematic circuit diagram of silicene-based 2-input NAND gate (Lint = 1 μm) with its input (blue) and corresponding output waveforms (red).
Fig 7.
Schematic circuit diagram of silicene-based 2-input NOR gate (Lint = 1 μm) with its input (blue) and corresponding output waveforms (red).
Fig 8.
Propagation delay (tp) and average power (Pavg) of silicene-based digital logic circuits with varying interconnect length (Lint).
INV, NAND2 and NOR2 represent inverter, 2-input NAND and 2-input NOR gates, respectively.
Fig 9.
(a) PDP and (b) EDP of silicene-based digital logic circuits. INV, NAND2 and NOR2 represent inverter, 2-input NAND and 2-input NOR gates, respectively.
Fig 10.
Comparison of propagation delay (tp) between the proposed silicene-based logic circuit with recent published results.
INV and NAND2 represent inverter and 2-input NAND gates, respectively.