Fig 1.
Overview of the proposed methodology.
Fig 2.
Block diagram of auxiliary circuit.
Fig 3.
Detailed proposed methodology.
Fig 4.
Total error approximation miter example.
Table 1.
Evaluation of 8-bit approximate adder library.
Table 2.
Evaluation of 16-bit approximate adder library.
Fig 5.
Plots of number of gates in miter vs. CPU time for 8-bit and 16-bit adders.
Fig 6.
Plots of maximum error rate vs. CPU time for 8-bit and 16-bit adders.
Fig 7.
Plots of average-case error vs. CPU time for 8-bit and 16-bit adders.
Fig 8.
Plots of number of errors vs. CPU time for all benchmarks.