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Fig 1.

Block diagram of the proposed HVG.

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Fig 1 Expand

Fig 2.

Schematic diagram of the current-starved ring oscillator (CSRO).

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Fig 2 Expand

Fig 3.

Schematic diagram of the proposed CTS based CP circuit.

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Fig 3 Expand

Fig 4.

Block diagram of the voltage regulator.

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Fig 4 Expand

Fig 5.

Schematic diagram of the proposed HVG circuit.

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Fig 5 Expand

Fig 6.

Die layout of the proposed HVG circuit without pads.

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Fig 6 Expand

Fig 7.

Chip layout of the proposed HVG with input/output pads.

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Fig 7 Expand

Fig 8.

Post layout simulation output for the proposed HVG circuit.

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Fig 8 Expand

Fig 9.

Simulated output ramp-up time for the proposed HVG circuit.

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Fig 9 Expand

Fig 10.

Simulated output ripple voltage of the proposed HVG.

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Fig 10 Expand

Table 1.

Performance comparison of the different HVG circuits.

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Table 1 Expand

Fig 11.

Corner analysis of the proposed HVG circuit.

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Fig 11 Expand

Fig 12.

Monte Carlo simulation result for the proposed HVG.

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Fig 12 Expand