Fig 1.
(a) Transmitter-Receiver analogy of a QDI/non-QDI (relative-timed) asynchronous circuit stage, and (b) technical schematic portraying the example RTZ and RTO completion detectors for the presumed dual-rail data bus comprising inputs (X1, X0), (Y1, Y0) and (Z1, Z0). The OR and AND gates used in the RTZ and RTO completion detectors are duals of each other. The datapath is highlighted by the red dashed line in (b).
Fig 2.
Input-output timing relation of different QDI circuits corresponding to (a) RTZ handshaking, and (b) RTO handshaking. Early set and reset behaviors of the early output circuit type are highlighted by the dotted green ovals in (a) and (b).
Fig 3.
(a) 32-bit QDI BCLA, and (b) 32-bit QDI BCLARC. The architectures remain the same for RTZ and RTO handshaking. The critical paths traversed for the application of data and spacer also remain the same for RTZ and RTO handshaking. One non-redundant lookahead carry output is produced by each 4-bit QDI BCLG in (a), whereas a non-redundant lookahead carry output and a redundant lookahead carry output is produced by each 4-bit QDI BCLGRC in (b). FA refers to the full adder and XOR3 refers to the 3-input XOR function, and both these belong to (QDI) early output type.
Fig 4.
(a) Proposed QDI 4-bit BCLG/BCLGRC, (b) early output QDI full adder, and (c) early output QDI XOR3 function. All the circuits correspond to 4-phase RTZ handshaking. Note that if the circuit portion shown in red is omitted in (a), it is called 4-bit BCLG; if the circuit portion shown in red is included in (a), it is called 4-bit BCLGRC–this interpretation of 4-bit BCLG and 4-bit BCLGRC is also applicable to Fig 5(a). The circuit portion shown in green lines signifies the internal completion detection.
Fig 5.
(a) Proposed QDI 4-bit BCLG/BCLGRC, (b) early output QDI full adder, and (c) early output QDI XOR3 function. All the circuits correspond to 4-phase RTO handshaking. The circuit portion shown in green lines signifies the internal completion detection.
Table 1.
Design metrics of several 32-bit asynchronous adders (QDI and non-QDI) corresponding to RTZ handshaking.
Table 2.
Design metrics of several 32-bit asynchronous adders (QDI and non-QDI) corresponding to RTO handshaking.
Table 3.
Areas of various asynchronous building blocks (in μm2) used in diverse adder architectures based on a 32/28nm CMOS process [43].
Fig 6.
Plots of normalized values of (a) CT and (b) PCTP of several 32-bit asynchronous adders corresponding to RTZ handshaking. The adder legends are referenced in Table 1. The red bar in (b) corresponds to the proposed 32-bit BCLARC (Z25) which is energy-efficient than the rest.
Fig 7.
Plots of normalized values of (a) CT and (b) PCTP of several 32-bit asynchronous adders corresponding to RTO handshaking. The adder legends are referenced in Table 2. The red bar in (b) corresponds to the proposed 32-bit BCLARC (O25) which is energy-efficient than the rest.