Fig 1.
MOSCAP Structure used in this work (Device Cross Section).
Table 1.
Atomic Layer Deposition Process Conditions for HfSiO and TiN Ultra-Thin Layers to fabricate the device structure.
Fig 2.
Leakage Resistance and I-V characteristics for different annealing temperatures.
(a) Leakage Resistance at different annealing temperatures. (b) I-V characteristic curve for 600°C. (c) I-V characteristic curve for 700°C. (d) I-V characteristic curve for 800°C. (e) I-V characteristic curve for 900°C. (f) I-V characteristic curve for 1000°C.
Fig 3.
C-V Hysteresis for samples at different annealing Temperatures.
(a) C-V profiles at different annealing ranging from 600 to 1000°C. (b) C-V profiling for 600°C. (c) C-V profiling for 700°C. (d) C-V profiling for 800°C. (e) C-V profiling for 900°C. (f) C-V profiling for 1000°C.
Fig 4.
Doping profile and Built in voltage as a function of Annealing Temperature.