Fig 1.
The HPMA architecture.
Fig 2.
The Frequent Two-Byte Subpattern Search (FTBSS) algorithm.
Fig 3.
Table construction algorithm.
Fig 4.
Pre-filtering algorithm.
Fig 5.
Pre-filtering procedure example.
Table 1.
Required amounts of memory for the pre-filter.
Table 2.
Hardware configuration for experiments.
Table 3.
Pattern length distribution.
Table 4.
Thread assignments to CPU cores.
Fig 6.
Throughput plotted against number of threads.
(a) HPMA-AC (b) HPMA-KMP (c) AC-CPU (d) KMP-CPU.
Fig 7.
Throughput plotted against pattern set size.
(a) HPMA-AC (b) HPMA-KMP (c) AC-CPU (d) AC-GPU (e) KMP-CPU (f) KMP-GPU.
Fig 8.
All algorithm throughput values plotted against intrusive packet percentages.
Fig 9.
Normalized throughput values plotted against intrusive packet percentages.
Table 5.
Theoretical ppayload values for various pattern set sizes.
Table 6.
Comparison of practical ppayload and theoretical ppayload values.
Table 7.
Required pre-filtering memory sizes for various pattern set sizes.
Table 8.
Statistics of the Defcon and web traffic traces.
Table 9.
All algorithm throughput values (in Gbps) using Defcon and web traffic traces.
Fig 10.
Energy consumption values plotted against intrusive packet percentages.
Fig 11.
Energy efficiency values plotted against intrusive packet percentages.