Fig 1.
Two bus network.
Fig 2.
Line stability index in PSCAD (a) Lmn, (b) LQP and (c) VCPI.
Table 1.
Categories of load buses for IEEE 14 bus system under base case and load increase information for PQ load increment.
Table 2.
Categories of load buses for IEEE 39 bus system under base case and load increase information for PQ load increment.
Fig 3.
Flow chart of the proposed approach.
Fig 4.
UPFC model.
Fig 5.
IEEE bus system network with UPFC in the location identified varying PQ load (a) IEEE 14 bus system and (b) IEEE 39 bus system.
Fig 6.
Index values of all the transmission lines for IEEE 14 bus system at nominal loading condition.
Fig 7.
Index values for different VSIs (a) for line 9–14 of IEEE 14 bus system with respect to time (b) for line 9–14 of IEEE 14 bus system with respect to number of PQ load increment and (c) for all transmission lines of IEEE 14 bus system for maximum PQ load increment.
Fig 8.
Index values of all the transmission lines of IEEE 39 bus system for nominal load.
Fig 9.
Index values of (a) line 9–8 for different VSIs with respect to time, (b) line 19–16 for different VSIs with respect to time, (c) line 9–8 for different VSIs with respect to number of PQ load increment and (d) line 19–16 for different VSIs with respect to number of PQ load increment.
Fig 10.
Index values of all transmission lines of IEEE 39 bus system for maximum PQ load increment.
Table 3.
Categories of load buses for IEEE 14 bus system under base case and load increase information for Q load increment.
Fig 11.
Index values for different VSIs (a) for line 13–14 of IEEE 14 bus system with respect to time, (b) for line 13–14 of IEEE 14 bus system with respect to number of Q load increment and (c) for all transmission lines of IEEE 14 bus system for maximum Q load increment.
Table 4.
Categories of load buses for IEEE 39 bus system under base case and load increase information for Q load increment.
Fig 12.
Index values for different VSIs (a) for line 9–8 with Q load increment, (b) for line 15–16 with Q load increment, (c) for line 9–8 with respect to number of Q load increment and (d) for line 15–16 with respect to number of Q load increment.
Fig 13.
Index values of all transmission lines of IEEE 39 bus system for maximum Q load increment.
Fig 14.
(a)Voltage across bus 9, (b) voltage across bus 14, (c) reactive power flow through line 9–14 and (d) real power flow through line 9–14 of IEEE 14 bus system.
Fig 15.
Index values of line 9–14 of IEEE 14 bus system.
Fig 16.
Voltage profile across all the buses of IEEE-14 bus network with UPFC placement in the line 9–14.
Fig 17.
(a) Voltage across bus 8, (b) Voltage across across bus 9, (c) Voltage across bus 16 and (d) Voltage across bus 19 of IEEE 39 bus system.
Fig 18.
(a) reactive power flow through line 9–8, (b) real power flow through line 9–8, (c) reactive power flow through line 19–16 and (d) real power flow through line 19–16 of IEEE 39 bus system.
Fig 19.
Index values of (a) line 9–8 and (b) line 19–16 of IEEE 39 bus system.
Fig 20.
Voltage profile across all the buses of IEEE-39 bus network with UPFCs placement in lines 9–8 and 19–16.
Fig 21.
(a) Voltage across bus 13, (b) voltage across bus 14, (c) reactive power flow through line 13–14 and (d) real power flow through line 13–14 of IEEE 14 bus system.
Fig 22.
Index values of line 13–14 of IEEE 14 bus system.
Fig 23.
Voltage profile across all the buses of IEEE-14 bus network with UPFC placement in the line 13–14.
Fig 24.
(a) Voltage across bus 8, (b) Voltage across bus 9, (c) Voltage across bus 16 and (d) Voltage across bus 15 of IEEE 39 bus system.
Fig 25.
(a) reactive power flow through line 9–8, (b) real power flow through line 9–8, (c) reactive power flow through line 15–16 and (d) real power flow through line 15–16 of IEEE 39 bus system.
Fig 26.
Index values of (a) line 9–8 and (b) line 15–16 of IEEE 39 bus system
Fig 27.
Voltage profile across all the buses of IEEE-39 bus network with UPFCs placement in lines 9–8 and 15–16.
Table 5.
Voltage profile improvement after placing UPFCs in IEEE—14 bus system by implementing VSIs both in dynamic and static modes.
Table 6.
Loading capability improvement after placing UPFCs in IEEE-14 bus system by implementing VSIs both in dynamic and static modes.
Table 7.
Voltage profile improvement after placing UPFCs in IEEE—39 bus system by implementing VSIs both in dynamic and static modes.
Table 8.
Loading capability improvement after placing UPFCs in IEEE—39 bus system by implementing VSIs both in dynamic and static mode.