Figure 1.
Figure 2.
Double-tail latch-type voltage sense amplifier.
Figure 3.
Self-calibrating comparator.
Figure 4.
Schematic diagram of the track and latch comparator (a) conventional track and latch comparator (b) small signal model of the comparator.
Figure 5.
Lewis-Gray comparator.
Figure 6.
Schematic diagram of the proposed differential pair dynamic latch comparator with S-R flip-flop.
Table 1.
Transistor dimensions used in this proposed topology.
Figure 7.
Transient simulation of the comparator input signals, VLATCH signal and output signals (SWP and SWM) using Virtuoso Spectre.
Figure 8.
Post-layout simulation results for average current of dynamic latch comparator.
Figure 9.
Propagation delay waveform between the VLATCH and SWP signal.
Figure 10.
Corner analysis of the comparator input/output signals.
Figure 11.
Pre-layout Monte-Carlo simulation result for the proposed design.
Figure 12.
Core circuit layout diagram of the proposed dynamic latch comparator.
Figure 13.
Post-layout Monte-Carlo simulation of the proposed dynamic latch comparator.
Table 2.
Performance comparison of the proposed dynamic latch comparator.