Figure 1.
CPU-GPU hybrid hardware platform.
The communication between the host (CPU) and device (GPU) is through a PCI-e bus.
Figure 2.
The work flow of the proposed framework.
There are four steps: data acquisition, image preprocessing, network construction and network analysis. We accelerate the latter two steps (shown in detail in the two blocks at the bottom). In network construction, correlation matrices for each subject are obtained by calculating Pearson’s Correlation coefficients. These correlation matrices are then “binarized” into adjacency matrices. In network analysis, several characteristics are calculated. Procedures denoted in green (i.e., Pearson’s Correlation, Partition and APSP) are accelerated with the GPU. Other procedures are implemented with multi-threads on a multi-core CPU.
Figure 3.
The process of the blocked Floyd-Warshall algorithm in a round.
(a) Illustration of which phase each block belongs to. In a certain round, Phase 1 is a primary block. Blocks that share the same row or the same column with the primary blocks are in Phase 2. All of the other blocks are in Phase 3. (b) Updating the dotted block requires two source blocks: 1) the block in the same column as itself and in the same row as the primary block, denoted with vertical lines, and 2) the block in the same row with itself and in the same column with the primary block, denoted with horizontal lines. Because we store only the upper block triangular matrix, some source blocks in Phase 3 do not exist, in which case we transpose the corresponding existing blocks to serve as the source blocks.
Figure 4.
Flow Chart of our GPU implementation of Newman’s Modular Detection Algorithm.
Each time, a module is dequeued. If β >0, the module is divided and the two new modules are enqueued. Repeat the process until the queue becomes empty.
Table 1.
A comparison of the time consumed between our hybrid framework and a single-thread CPU implementation.
Figure 5.
Performance of different APSP algorithms on different platforms.
The blue line corresponds to the 8-thread BFS algorithm on the quad-core CPU, which is suitable for sparse networks. Its running time is proportional to the sparsity. The black line corresponds to the blocked FW algorithm on the GPU, which is suitable for dense networks. Its running time is irrelevant to the sparsity. The intersection point of the two lines is approximately where the sparsity equals 2%. This criterion is guidance for making the choice.
Table 2.
Running time for computing each network metric on the CPU, GPU and CPU-GPU hybrid.
Table 3.
Small-world properties of brain networks, and a comparison with random networks.
Figure 6.
The modular structure of brain networks under six sparsities.
The brain is divided into 48, 22, 46, 46, 46, and 52 modules with Q = 0.88, 0.72, 0.86, 0.84, 0.81, and 0.74 in real networks and with a sparsity of 0.023%, 0.033%, 0.047%, 0.067%, 0.098%, and 0.151%, respectively. This figure was visualized with the BrainNet Viewer (http://www.nitrc.org/projects/bnv/).
Figure 7.
Distribution of the nodal degree under 6 sparsities (log-log plot).
Panel (a)∼(f) are the degree distribution and the fitting result of the network with a sparsity of 0.023%, 0.033%, 0.047%, 0.067%, 0.098%, and 0.151%, respectively. The spot lines reflect the probability of finding a node connected to a given number of neighbors; the red solid lines indicate the curve fitted results of the power law . The estimated exponent γ under 6 sparsities are 4.16, 3.21, 2.80, 2.61, 2.46 and 2.16, respectively.
Figure 8.
The degree of voxels near the cerebral cortex under different sparsities.
Nodes that have a much higher degree than average are considered to be potential hub-voxels. We mark the voxels with degrees that are one standard deviation above the mean. Voxels with a higher degree are in yellow, and voxels with a lower degree are in red. Across different sparsities, some hub-areas are stable, including the bilateral precuneus (PCUN) and posterior cingulate cortex (PCC), the medial prefrontal cortex (MPFC), the lateral prefrontal cortex (LPFC), and the inferior parietal lobule (IPL) (containing the angular gyrus and the supramarginal gyrus). This figure was visualized with the BrainNet Viewer (http://www.nitrc.org/projects/bnv/).