Figure 1.
(A) Truth table for a binary half adder. (B) Oscillator circuit diagram for a binary half adder comprising two inputs and
and two oscillators
and
. The sum oscillator
will oscillate if either
or
are active. The carry oscillator
will oscillate if both
and
are active. An inhibitory connection from
to
suppresses oscillator
if
is active.
Figure 2.
(A) Truth table for a binary full adder. (B) Oscillator circuit diagram for a binary full adder comprising three inputs and
and two oscillators
and
. Oscillator
will oscillate if either
or
are active. Oscillator
will oscillate if any two of
and
are active. An inhibitory connection from
to
suppresses oscillator
if
is active, however, the inhibition is only sufficient to suppress
for
. For inputs of
the total input to
is still sufficient to induce oscillation.
Figure 3.
Phase portrait for Fitzhugh-Nagumo model with and
shown for two input strengths
and
.
From an initial resting state at , the transient dynamics is of a wide trajectory before settling onto a limit cycle.
Figure 4.
Associated time series of and
for corresponding Fig. 3.
Note that after transients, (A) for
and
, (B) whereas
.
Figure 5.
Time series for Fitzhugh-Nagumo binary half adder.
The parameter values taken for the transfer function , see Eq. (5), are
and
. All binary combinations of oscillatory inputs
and
give the required binary outputs
and
(see Fig. 1A). Here
represents the sum and
the carry in terms of standard logical circuitry. The observed pulse like behavior after switching is due to the wide trajectories taken by the input oscillators after being perturbed from the resting state.
Figure 6.
Time series for a Fitzhugh-Nagumo two oscillator full adder.
All binary combinations of oscillatory inputs ,
and
give the required binary outputs for
and
(see Fig. 2A). The weights used in this example were again
,
and
(see Eq. (4)).
Figure 7.
Seven input, three oscillator full adder.
(A) Block diagram for seven input, three oscillator full adder. (B) Time series for a Fitzhugh-Nagumo three-oscillator full adder. The total input strength is shown in the first row. All binary combinations of oscillatory inputs
to
give the required binary outputs for
,
and
. The weights used in this example were
,
,
,
,
and
, where
is the inhibitory connection from
to
,
is from
to
and
is from
to
. Note that the amplitude of oscillation increases when the sum of the input to any oscillator is greatly above threshold, however, the binary on/off response is as required.
Figure 8.
(A) Truth table for bit binary multiplier. (B) Schematic of the binary oscillator
bit multiplier using oscillators based on standard circuitry.
Figure 9.
Time series of a bit multiplier using oscillators based on standard circuitry.
All possible binary combinations for inputs and
are shown. The oscillators
and
represent binary digit representation of the powers of
. Oscillators
and
are used in the internal circuitry only and their time traces have been made fainter to emphasize the binary output oscillators. For example, at time
the inputs
representing the decimal
and
, representing the decimal
, giving an output where
and
are oscillating, being the binary equivalent
of the decimal
. Note
and
are not oscillating. This is equivalent to column eight above and row eight in the truth table Fig. 8A.
Figure 10.
Schematic of an SR flip flop using oscillators.
Both oscillators and
receive an external input current
and there are inhibitory connections
between the oscillators. From an initial state where one oscillator is active the other will remain suppressed. External inputs
or
to the inactive oscillator will induce a switch. The oscillators are effectively performing NOR logical operations as in a conventional SR NOR latch.
Figure 11.
Time series of an SR flip-flop using oscillations to switch.
(A) Simulation with and
. The simulation is initialized using a single external current to
for
. At
, oscillator
also receives an external input current, however, it is suppressed by the output from
. The initial state has
active and
inactive. A continuous switching pulse is provided by
at
. At
, this switching pulse is turned off, but
and
remain in the switched state (as required). A further switch is performed at
using a continuous pulse to
. (B) Time series of an SR flip-flop using single input pulses to switch, with
and
. The switching is performed as for case A, however, only one pulse cycle (ballistic propagation) is used. Note the switching occurs as required and the system remains switched once the pulse has been received.
Figure 12.
Controlled switching in the presence of noise.
(A) and (B) Time series of SR flip-flop as in Fig. 11 with additional Gaussian noise, mean = , standard deviation =
, added to all oscillators. In both cases the switching occurs as required.