## Figures

## Abstract

Quantum computing is a newly emerging computing environment that has recently attracted intense research interest in improving the output fidelity, fully utilizing its high computing power from both hardware and software perspectives. In particular, several attempts have been made to reduce the errors in quantum computing algorithms through the efficient synthesis of quantum circuits. In this study, we present an application of an optimization model for synthesizing quantum circuits with minimum implementation costs to lower the error rates by forming a simpler circuit. Our model has a unique structure that combines the arc-subset selection problem with a conventional multi-commodity network flow model. The model targets the circuit synthesis with multiple control Toffoli gates to implement Boolean reversible functions that are often used as a key component in many quantum algorithms. Compared to previous studies, the proposed model has a unifying yet straightforward structure for exploiting the operational characteristics of quantum gates. Our computational experiment shows the potential of the proposed model, obtaining quantum circuits with significantly lower quantum costs compared to prior studies. The proposed model is also applicable to various other fields where reversible logic is utilized, such as low-power computing, fault-tolerant designs, and DNA computing. In addition, our model can be applied to network-based problems, such as logistics distribution and time-stage network problems.

**Citation: **Jung J, Choi I-C (2021) A multi-commodity network model for optimal quantum reversible circuit synthesis. PLoS ONE 16(6):
e0253140.
https://doi.org/10.1371/journal.pone.0253140

**Editor: **Thippa Reddy Gadekallu,
Vellore Institute of Technology: VIT University, INDIA

**Received: **April 8, 2021; **Accepted: **June 1, 2021; **Published: ** June 22, 2021

**Copyright: ** © 2021 Jung, Choi. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

**Data Availability: **The direct link to the files used in our experiments is http://www.informatik.uni-bremen.de/rev_lib/functions.php, click “download all functions” to download all necessary files. The data can also be accessed through RevLib database, http://revlib.org/index.php, then by clicking “all functions.”

**Funding: **This research was supported by the Basic Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Science and ICT(MSIT).(No. 2020R1A4A307986411) This research was also supported by the NRF grant funded by the Korea government(MSIT). (No. 2017R1E1A1A0307098814) Both funding is received by professor IC Choi, the corresponding author. The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. National Research Foundation of Korea(NRF): https://www.nrf.re.kr/eng/index Ministry of Science and ICT(MSIT): https://english.msit.go.kr/eng/index.do.

**Competing interests: ** The authors have declared that no competing interests exist.

## Introduction

Quantum computing is a next-generation computing paradigm based on the uncertainty 2 principle underlying quantum mechanics. This new technology has recently attracted attention owing to its high computing power compared to classic computing environments. Quantum computing enables efficient calculation for certain difficult nondeterministic polynomial time (NP) problems such as prime factorization and discrete logarithms [1].

The most significant feature of a quantum computer, differing from a traditional computer, is an information unit called a *quantum bit* or *qubit*. Qubits are based on quantum superposition and quantum entanglement, which are fundamental properties in quantum mechanics. Compared to *bits* in a traditional computing environment, qubits can contain an exponentially large amount of information even with the same number of information units.

Considerable research has been conducted to enhance the practicality of quantum computing in terms of hardware [2, 3] and software. In particular, a wide range of research has been proposed regarding software, from basic to applicational quantum algorithms. For example, basic quantum algorithms include Grover’s algorithm [4] for an unstructured search, Shor’s algorithm [5] for integer factorization, and the Harrow–Hassidim–Lloyd algorithm [6] for simultaneous linear systems. Some applicational algorithms include a quantum genetic algorithm [7], quantum support vector machine [8], quantum principal component analysis [9], and quantum reinforcement learning [10]. Research has also been conducted on applying quantum computing environments to real-world problems such as chemistry [11] and data science [12].

Despite the advantages of quantum computing, computational accuracy is still insufficient for practical use. The major factors that cause computational errors are the qubit and quantum gates. A qubit is implemented using elementary particles such as electrons and photons that maintain stability for only a short period of time [13]. A quantum gate applies a specific operation on the qubit, and this process is implemented as physical stimuli such as a pulse wave. The more often these stimuli are applied to the qubit, the less stable the qubit becomes, increasing the computational error. To overcome the intrinsic hardware issues, research attempts have been made in terms of software development. As a part of these attempts, many studies have been conducted on the design of efficient circuits for quantum computing.

Various metrics for evaluating the circuit efficiency for quantum computing have been proposed. These metrics include the number of gates, computational speed, quantum cost, qubit interaction cost, number of auxiliary qubits, and circuit depth [14]. The quantum cost refers to the total number of basic quantum gates required to implement a logical gate in the quantum computing environment. Thus, it indicates the actual implementation cost of a logic gate or a circuit. Several studies have also been conducted on cost systems for various logic gates and quantum circuits [15, 16].

Based on the presented metrics, various studies have developed methodologies for an efficient circuit synthesis of reversible functions in the quantum computing environment. Most early studies present methodologies based on observations and preconfigured circuit libraries. Methodologies for large-sized reversible functions have been proposed using a template matching approach that exploits a library of small-scale circuits [17–19]. Research has also been conducted to perform post-optimization on the synthesized circuit through a relocation algorithm [20, 21]. However, these methodologies do not guarantee the optimality of the synthesized circuit.

A circuit synthesis methodology based on the systematic searching method has also been proposed. An algorithm to minimize the gate count through a decomposition of a Boolean reversible logic is proposed based on the cycle representation of a given logic [22]. A heuristic algorithm to improve the quantum cost has been considered, which uses the Reed–Muller decomposition to express a binary reversible function as the sum of the products of binary variables [23, 24]. A neighbor searching scheme on exclusive-sum-of-products based reversible logic has also been proposed [25]. A methodology based on binary decision diagrams was developed to handle relatively sizeable reversible circuits [26, 27, 28]. A synthesis algorithm based on the functional decision diagrams and dependency diagrams is also presented [29]. A circuit synthesis using the A* algorithm, a searching scheme based on the shortest path in the search graph, has also been proposed [30]. Most of these heuristic-based approaches can be applied to relatively large-scale problems. However, such algorithms are not guaranteed to obtain optimal results and present challenges when additional constraints are considered. Some post-optimization algorithms have been proposed [31–34] to overcome the shortcomings of the heuristic-based approach.

A methodology was also developed to guarantee the optimality in the number of gates through the satisfiability problem [35]; however, the problem size that the proposed methodology can solve is limited. Furthermore, the number of gates is insufficient to represent a practical cost system in implementing reversible circuits in a quantum computing environment. Several approaches have been presented to search for near-optimal circuits based on evolutionary algorithms such as adaptive genetic algorithms [36] and genetic programming [37]. However, owing to the inherent characteristics of metaheuristics, they cannot guarantee the optimality of the solution. In addition, consideration of additional constraints and objective functions is difficult. In our previous study, we proposed an optimization model to obtain a reversible circuit of the minimal quantum cost [38]. The model uses a complicated external function based on the gate pattern, and hence, the size of the problem that the model can handle is limited to a small scale.

In this study, by accommodating the complex external functions into the model, the proposed model is far more structured compared to our previous approach [38]. For this improvement, we adopt a well-known multi-commodity network flow problem to provide the basic framework for the improved model. Since the 1960s, various studies have applied their designed models to this problem [39]. For famous large-scale optimization techniques such as column generation [40], Benders decomposition [41], and Dantzig–Wolfe decomposition [42], the multi-commodity network flow problem is considered a best-practice example because of its well-defined constraint structure. Several solution methodologies have also been proposed for multi-commodity network flow models such as the parallelized cost decomposition algorithm [43] and the cost reoptimization algorithm [44]. Various studies have been conducted to apply multi-commodity network flow models to practical problems. For example, the model has been applied to fields such as transportation [45], scheduling [46], and production planning [47].

This study is aimed at the development of a novel optimization-based approach for a circuit synthesis of reversible functions with an optimal quantum cost as a methodology in a more robust fashion. Our study is different from previous studies in that the proposed model can evaluate the optimality of a solution and is free to consider additional constraints and objective functions. These differences arise because the proposed methodology is based on an optimization model. Specifically, the proposed model is based on an extended version of the multi-commodity network flow model, which is combined with an arc selection problem of the underlying network. Because the proposed model has a straightforward structure based on the existing well-known problems, it shows better computational results and has the advantage of being a versatile model that can consider additional constraints or be applied to other fields. Quantum algorithms generally adopt a Boolean reversible logic as a key element that often represents the problem to solve [48]. Accordingly, various types of reversible logic need to be circuited. Motivated by this need, our research presents an efficient synthesis methodology of circuits for Boolean reversible logic. A library of logic gates, referred to as a multiple control Toffoli gate, is used for the circuit representation.

### Contributions

This research has two major contributions. First, our optimization-based approach on quantum reversible circuit synthesis is a novel attempt with high robustness from the perspective of reversible circuit synthesis and quantum computing.

Compared to previous model-based studies that minimize the number of gates, our model handles the objective that minimizes the quantum cost of reversible circuits, which implies an actual implementation cost required in a quantum computing environment. Additional constraints can also be freely added to the model according to the user’s purposes or technical issues. In addition, our optimization-based approach guarantees the optimality of the solution and can thus be utilized as the baseline methodology for evaluating circuit synthesis heuristics. Second, we propose an optimization model based on an extension of the multi-commodity network flow model that uniquely appears in the target problem. Compared to a conventional multi-commodity network flow model, where the network cost is defined for each unit flow, the network cost of our model is defined according to the subset of selected arcs. As mentioned earlier, the multi-commodity network flow model is a well-known model with rich theoretical and applicational studies, which allows us to continue further research on the proposed model. Furthermore, the proposed model yields significantly better computational results compared to previous studies. The optimal circuits presented in this study can also be exploited as building blocks to synthesize large-scale circuits.

Furthermore, the proposed model has high applicability to other areas. The reversible circuit synthesis methodology presented in this study can be applied not only to quantum computing but also to other fields that exploit reversible logic, such as low-power computing, fault-tolerant design, nanotechnology, DNA computing, and optical computing [49]. The proposed model, which is an extended form of a multi-commodity network flow model, can also be applied to conventional network problems such as a distribution and time-stage network.

The rest of this paper is organized as follows. In the *Materials and methods* section, we introduce the background concepts and terminologies used in this paper. A detailed description of the target problem, referred to as the quantum reversible circuit synthesis (QRCS) problem, is presented in the following section. The mathematical model for the target problem is described in Section 4. Section 5 shows the computational results of the proposed optimization model on the benchmark datasets. Section 6 presents some concluding remarks regarding this study and a direction for future research.

The rest of this paper is organized as follows. In Section 2, we introduce the background concepts and terminologies used in this paper. A detailed description of the target problem, referred to as the quantum reversible circuit synthesis (QRCS) problem, is presented in the following section. The mathematical model for the target problem is described in Section 4. Section 5 shows the computational results of the proposed optimization model on the benchmark datasets. Section 6 presents some concluding remarks regarding this study and a direction for future research.

## Materials and methods

### Background concepts and terminologies

This subsection is largely divided into four parts: quantum computing, Boolean reversible functions, reversible logic gates, and the multi-commodity network flow model. Here, we describe the basic concepts and terminologies used in each topic, as well as the mathematical notation.

#### Quantum computing.

A *quantum bit* or *qubit* is an elementary unit used in the quantum computing environment. It is often physically implemented with a quantum system such as an electron, ion, or photon. When multiple qubits are considered a single entity, it is called a *qubit register*. A single qubit saves the probabilistic information of one of the two deterministic states measured when one observes the qubit. These two pure states are called *computational basis states*.

**Definition 1**. A single qubit retains *two computational basis states*(*CBSs*), a 0 state, and a 1 state, which are respectively represented as |0〉 and |1〉, following a bra-ket notation. Both CBSs can also be denoted by two-dimensional unit vectors, as shown in Eq (1).
(1a) (1b) (1c)

The notation in Definition 1 can be extended to a qubit register. In a 2-qubit system, the total number of combinations of measurable states is 2^{2} = 4 because both qubits have two CBSs each. In this case, the qubit register has a total of four CBSs: |00〉, |01〉, |10〉, and |11〉. Each binary digit corresponds to the states of the qubit. These CBSs can also be represented as a set of four-dimensional vectors as shown in Eq (1b). For the generalized case of a qubit register with *N* qubits, a total of 2^{N} CBSs are formed: |0⋯00〉, |0⋯01〉, ⋯, |1⋯10〉, |1⋯11〉. The binary sequence in the bra-ket notations is composed of *N* digits, which correspond to each of *N* qubits. Eq (1c) shows that each CBS can also be represented as a 2^{N} dimensional unit vector.

As mentioned earlier, the qubit saves the probabilistic information of multiple CBSs simultaneously. All of these possible states that a qubit system can represent are called *quantum states*.

**Definition 2**. A *quantum state* |*ψ*〉 of a qubit or a qubit register is the linear combination of all CBSs with complex scalars , ∀*i* = 1, ⋯, 2^{N}. Eq 2a shows the general form of a quantum state of *N*-qubit registers.
(2a) (2b)
The squared Euclidean norm of each coefficient implies the measurement probability of the corresponding CBS when one observes a qubit or a qubit register. Therefore, Eq (2b) implies that the sum of all measurement probabilities equals 1.

To change the given quantum state to a desired state, a sequence of *basic quantum gates* is adopted and a quantum algorithm is composed.

**Definition 3**. A *basic quantum gate* is a unit device that physically realizes a unitary operation on a target qubit. The unitary operation is represented as a unitary matrix *U* of size 2^{N} × 2^{N} in an *N*-qubit system, where *UU*^{†} = *I* when *U*^{†} is the conjugate transpose of *U*.

*Example 1*. Eqs (3a) and (3b) show an algebraic operation of a Pauli *X* gate, a well-known basic quantum gate. As presented in Eq (3a), a Pauli *X* gate is represented as a 2 × 2 unitary matrix *U*_{X}. It should be noted that *U*_{X} is a permutation matrix. In Eq (3b), a Pauli *X* gate conducts a unitary transformation *U*_{X} on a single qubit quantum state |*ψ*〉 = *α*_{1}|0〉 + *α*_{2}|1〉 for . The result of the transformation shows that the probabilities to observe |0〉 and |1〉 are exchanged with each other.
(3a)
(3b)

Various other quantum basic gates, such as the Hadamard gate and phase shift gates, are also frequently used in quantum computing. Some particular basic quantum gates, called *controlled gates*, such as controlled-*X* gates and controlled-*V* gates, operate jointly on multiple qubits.

**Definition 4**. A *controlled gate* is a type of basic quantum gate composed of a control bit and a target bit. In particular, a target bit is assigned with a basic quantum gate for a single qubit. A controlled gate activates the assigned basic quantum gate on a qubit corresponding to a target bit only when the qubit corresponding to the control bit is in state 1.

*Example 2*. A controlled gate with a Pauli *X* gate on its target bit is particularly called a *CNOT gate*(*controlled-NOT gate*). This example presents how a CNOT gate works on a 2-qubit system. Assume that a control bit is located on the first qubit and the target bit is located on the second qubit. In Eq (4a), a CNOT gate is represented as a 4 × 4 unitary matrix *U*_{CNOT}. It should be noted that *U*_{CNOT} is a permutation matrix. Eq (4b) shows an algebraic operation of a CNOT gate on a quantum state |*ψ*〉 = *α*_{1}|00〉 + *α*_{2}|01〉 + *α*_{3}|10〉 + *α*_{4}|11〉 for . The result shows that the probabilities of observing |10〉 and |11〉 are exchanged with each other.
(4a)
(4b)

A *quantum circuit* is a diagram that represents the quantum algorithm as a sequence of quantum gates interconnected by qubit wires. Fig 1 shows an example of a graphical representation of a quantum circuit. The example presents a specific form of a 4-qubit quantum circuit of Grover’s algorithm [50], a well-known quantum algorithm for an unstructured search.

A quantum circuit implementing Grover’s algorithm with four qubits [50].

Each of the four horizontal lines represents the qubits, whereas the initial state of each qubit is represented as the starting point of each qubit wire. The objects located on the wires represent a quantum gate that performs a unitary transformation on the quantum states of the corresponding qubits. Some gates are located across multiple qubits with black circles on a few of the qubits. These are a type of controlled gate, and the black circles denote the control bits. After all gates are applied, the qubits are measured, and their quantum states collapse into one of the CBSs according to the measurement probability.

#### Boolean reversible functions.

All operations in quantum computing are unitary operations, according to Definition 3. Among numerous unitary operations, *Boolean reversible functions* are frequently exploited as a key component in quantum algorithms [48]. For example, Grover’s algorithm in Fig 1 consists of three phases: initialization, oracle, and amplification. Among these phases, the *oracle phase* is a key part of the algorithm embedding the information about the target problem [51].

**Definition 5**. A *reversible function* is a one-to-one and bijective function of a finite set. In other words, the reversible function is a permutation. In particular, a *Boolean reversible function* is a multi-output reversible function composed of binary inputs and outputs.

*Example 3*. A Boolean reversible function is represented in several ways. Assume that a Boolean reversible function *f*: (*x*, *y*, *z*) → (*x*, *y*, *xy* ⊕ *z*) is given. Table 1(a) shows a matrix *P*_{f} representing the Boolean reversible function *f*. The matrix representing the Boolean reversible function appears as a permutation matrix. The same function *f* can also be represented as a truth table, as shown in Table 1(b).

Boolean reversible functions can be classified into two types depending on the existence of the symbol “-” in the truth table: *completely specified function* and *incompletely specified function*.

**Definition 6**. We call the symbol “-” in the truth table an *unspecified bit*, which implies that the corresponding bit can be mapped either to 0 or 1. A *completely specified function* includes no unspecified bit on its truth table. Conversely, an *incompletely specified function* contains at least one unspecified bit in its truth table.

*Example 4*. Sample functions are shown in Table 2. Here, *peres* is a completely specified function, whereas *minialu* is an incompletely specified function. Note that if a given function is incompletely specified, the unspecified bits must be decided with either a 0 or 1 prior to the circuit implementation. At the same time, the output column must form a one-to-one correspondence with the input column because the given function is reversible.

#### Reversible logic gates.

Various types of gates, such as multiple control Toffoli gates, a multiple control Fredkin gate, and Peres gates, have been suggested to represent the Boolean reversible function in a circuit [14]. Among these types of gate libraries, a *multiple control Toffoli gate* is often introduced to express a Boolean reversible function.

**Definition 7**. A *multiple control Toffoli (MCT) gate* is a type of reversible logic gate that is composed of multiple control bits and a single target bit. The gate *C*^{m} *NOT*(*x*_{1}, ⋯, *x*_{m};*x*_{m+1}) implies an MCT gate with control bits on the first *m* lines and the target bit on the last *x*_{m+1} line. If all lines corresponding to control bits carry a state of 1, the line with the target bit flips the corresponding state of the qubit.

In a quantum circuit, a control bit is denoted as a black circle, whereas a target bit is denoted as a white circle. Note that for *m* = 0, 1, MCT gates are respectively equivalent to the Pauli *X* gate and the CNOT gate. When *m* = 2, the gate is called a Toffoli gate.

Most reversible logic gates cannot be implemented by single physical gates in a quantum computing environment. Thus, the reversible logic gate must be decomposed into a number of quantum basic gates. In the case of an MCT gate, as the number of control bits increases, the gate becomes more difficult to implement. Among several cost models for implementing a quantum circuit and a quantum gate, our study adopts a model called *quantum cost*.

*Quantum cost* refers to the number of basic quantum gates required to implement the given function. For example, a Toffoli gate *C*^{2} *NOT*(1, 2;3) can be decomposed into five quantum basic gates, as shown in Fig 2. This implies that the quantum cost of a Toffoli gate is 5 [15]. As mentioned earlier, when the number of control bits increases, the MCT gate becomes more difficult to implement with a higher quantum cost. Table 3 shows an increasing quantum cost as the number of control lines increases [35].

A circuit composed of five basic quantum gates implementing the Toffoli gate *C*^{2} *NOT*(1, 2;3).

#### Multi-commodity network flow model.

A *multi-commodity network flow (MCNF) model* is a well-known model in network optimization. The following formulation represents the MCNF model in the node–arc form. The model we propose in this study is also based on the following formulation structure. A set *N* denotes the set of all nodes in *G*, whereas *A* denotes the set of all arcs. A set *K* implies the set of all commodities consisting of commodity *k* with source node *S* and terminal node *T*. A parameter denotes the unit flow cost on an arc (*i*, *j*) and with the flow on arc (*i*, *j*). A parameter represents the supply and demand of commodity *k* at node *i*. Let *g*_{ij} be the arc capacity on arc (*i*, *j*), whereas denotes the flow capacity of commodity *k* on arc (*i*, *j*). Without a loss of generality, assume that each unit of each commodity consumes one unit of capacity from each arc upon which the commodity flows.
(5a) (5b) (5c) (5d)

Eq (5a) represents the objective function that minimizes the total cost required to carry the flow from the origin to the appropriate destination. Eq (5b) is a set of constraints that assign the given supply and demand to each node *i* and commodity *k*. Eq (5c) is a set of *bundle constraints* that assign the upper bound to the total flow of each arc. The last constraint in Eq (5d) guarantees a non-negative value to the decision variables for arc (*i*, *j*) and commodity *k* without exceeding the upper bound .

### Quantum reversible circuit synthesis (QRCS) problem

In this section, we define the *quantum reversible circuit synthesis (QRCS)* problem in detail and introduce the underlying MCNF structure with a few examples following the notation presented in Eqs (5a)–(5d).

#### Input and output of QRCS problem.

The input of the QRCS problem is a Boolean reversible function given in a truth table form. The output of the QRCS problem is a circuit composed of MCT gates (including a NOT gate and a CNOT gate), which is a realized version of a Boolean reversible function given as an input of the problem. The given Boolean reversible function can be realized as various feasible circuits of different versions. In particular, the resulting circuit must have the minimum quantum cost among these feasible circuits. The length of the states determines the number of qubits in the circuit in the given truth table. Moreover, the maximum number of MCT gates of the circuit is given to the model, thus limiting the size of the resulting circuit.

#### MCNF Representation of QRCS problem.

We formulate the model of the QRCS problem as an extended version of the MCNF model. The conventional MCNF model charges the unit flow cost per single arc. However, in the extended MCNF model that uniquely appears in the QRCS problem, the cost is given according to the selected subset of arcs.

*Terminologies*. Suppose that a Boolean reversible function *F* is realized as a circuit composed of *N*_{Q} qubits and *N*_{D} MCT gates. Let a network be a staged digraph composed of *N*_{D} + 1 successive *stages*. Each stage is composed of *state nodes*, which is labeled by a *N*_{Q}-bit binary string representing the corresponding CBS. All flows in the network start from *source node* *S* and sink into *terminal node* *T*. Every state node in the initial stage is given an inflow of a specific commodity type from the source node *S*. Each commodity represents *N*_{K} elements in the output column of the given truth table. We call the conceptual space where the arcs are generated as *levels*. There are three types of levels depending on the components on both sides. An *input level* denotes the level between the source node *S* and the first stage. A *gate level* implies the level between two adjacent stages. An *output level* exists between the last stage and the terminal node *T*. Fig 3 shows the terminologies introduced in network when *N*_{Q} = 3 and *N*_{D} = 2.

*Notations*. The notations used to represent the QRCS problem in the context of the MCNF model are presented in Fig 3. They follow the MCNF model presented in Eqs (5a)–(5d). The supply from the source node *S* of each commodity *k* is denoted as , whereas the demand required at terminal node *T* of each commodity *k* is denoted as . In the input level, the upper bound for each flow of the arc from source node *S* to the state node *σ* in stage 0 is denoted as for commodity *k*. For arc (*σ*, *π*) in gate level *d*, the upper bound for each flow of the arc is denoted as for commodity *k*. In the output level, the upper bound for each flow of the arc (*S*, *π*) for a state node *π* in stage *N*_{D} is denoted as for commodity *k*. Note that this demand parameter of each commodity enforces each flow carrying different commodities to arrive at the target state node in the final stage, resulting in an appropriate circuit realization of function *F*. Because all upper bounds of the flow are below 1, *g*_{ij} for every arc (*i*, *j*) in network is set to 1. These parameters are preliminarily determined by function *F* given in a truth table form. However, the cost parameter of network varies according to the selected network topology. In contrast to the original MCNF model, which includes a unit flow cost on each arc, the QRCS problem sets the network cost per gate assigned to each gate level. Therefore, instead of cost notation for each arc (*i*, *j*) and commodity *k*, we denote the gate cost for gate *G*_{d} in gate level *d* as *c*(*G*_{d}).

Some additional properties related to network topology are considered according to the characteristics of the QRCS problem. The properties are presented in the following three remarks.

**Remark 1**. An arc in network can only be generated between two nodes in the adjacent stages. This implies that network forms as a staged digraph.

**Remark 2**. An arc in the gate level of network can only be generated when the Hamming distance between the two state nodes is less than or equal to 1. The remark is derived from the fact that each MCT gate includes only one target bit. Note that the Hamming distance implies the number of bit positions where the two bits contain different characters.

**Remark 3**. A set of arcs in a single gate level must form a bijective connection between the two groups of nodes in adjacent stages. This remark implies that the arcs in the gate level directly represent the permutation of CBS that occur by the assigned MCT gate.

#### Logic for MCT gate-network conversion.

Each MCT gate *C*^{m} *NOT*(*x*_{1}, ⋯, *x*_{m};*x*_{m+1}) assigned to a single gate level is represented by a set of arcs denoting the permutation between the state nodes of two adjacent stages. The proposed model connotes the logic converting the assigned gate into a set of arcs in the network. Algorithm 1 shows the full logic as a pseudo code. The three conditions are nested to classify the cases into *CASE 1*, *CASE 2*, *CASE 3A* and *CASE 3B*.

**Algorithm 1**: MCT gate-network conversion

**for** *d*^{th} gate level for *d* ∈ {1, ⋯, *N*_{D}} **do**

Assign the gate *G*_{d} = *C*^{m} *NOT*(*x*_{1}, ⋯, *x*_{m};*x*_{m+1})

**if** no gate is assigned **then**

*CASE 1* (Empty gate)

**for** CBS *σ* in (*d* − 1)^{th} stage **do**

Generate an arc (*σ*, *σ*) on *d*^{th} gate level

**end**

**else**

**if** *m* = *0 for the gate* *G*_{d} **then**

*CASE 2* (NOT gate)

**for** CBS *σ* in (*d* − 1)^{th} stage **do**

Compute by performing the given NOT gate on *σ*

Generate an arc in *d*^{th} gate level

**end**

**else**

*CASE 3* (MCT gate)

**f**or CBS *σ* in (*d* − 1)^{th} stage **then**

Conduct *sync test*

**if** CBS *σ* has 1 in every digit *x*_{1}, ⋯, *x*_{m} **then**

*CASE 3A* (In sync with given MCT gate)

Compute by performing the given MCT gate on *σ*

Generate an arc in *d*^{th} gate level

**else**

*CASE 3B* (Not in sync with given MCT gate)

Generate an arc (*σ*, *σ*) in *d*^{th} gate level

**end**

**end**

**end**

**end**

**end**

The first two conditions classify the cases in terms of the gate level. The first condition of Algorithm 1 checks whether a gate is assigned to the corresponding gate level. If no gate is assigned, the case is denoted as *CASE 1*. As shown in the network example of Fig 4, there are no permutations between two adjacent stages in the state nodes. Note that *CASE 1* occurs when the total number of MCT gates assigned in the circuit is less than the total number of gate levels given in the network layout. The second condition checks if the assigned MCT gate contains the control bits. If the given gate has no control bits, then the gate is considered to be a NOT gate. This case is denoted as *CASE 2*, and the corresponding network represents the permutation of the given NOT gate, as shown in Fig 5. The arcs (000, 100), (001, 101), (010, 110), and (011, 111) are formed because the first bit of each input CBS must be flipped. The last classification is for MCT gates, including at least one control bit. In contrast to the classification for *CASE 1* and *CASE 2*, the final classification is applied from the perspective of the CBS, following the rule referred to as *sync test*.

**Definition 8**. The *sync test* of gate *C*^{m} *NOT*(*x*_{1}, ⋯, *x*_{m};*x*_{m+1}) checks whether a CBS has the quantum state |1〉 in every control qubits *x*_{1}, ⋯, *x*_{m}. If the CBS passes the test, the CBS is *in sync* with the given MCT gate.

Fig 6 shows an example of *CASE 3A*. The gate *C*^{1} *NOT*(1;2) and the input CBS 101 are given. The second bit of the CBS is flipped to 0 because the target bit is located on the second qubit. The network representation in Fig 6 also shows the corresponding change in state by forming arcs (101, 111) and (111, 101). Conversely, *CASE 3B* denotes the case in which the given CBS is not in sync with the assigned MCT gate. The example for CBS 001 is also given in Fig 7, which fails the sync test. Thus, the resulting state remains unchanged and the corresponding arc also makes no permutation. The logic in Algorithm 1 serves as the basic skeleton in developing the entire mathematical model, which is presented in the next section.

#### Descriptive examples.

*Example 5*. Fig 8 describes the MCNF representation of the QRCS problem when a completely specified function *F*_{1} with *N*_{Q} = 3 and *N*_{D} = 2 is given. Function *F*_{1} is given in Table 4 in a truth table form. Thus, the network is constructed using three stages, each composed of eight state nodes. Moreover, eight distinct types of commodities, *k* = 1, 2, ⋯, 8, originate from the source node *S* because function *F*_{1} is a completely specified function. The correspondence between the commodity index *k* and the output strings is presented in in Table 4. Table 4 also includes the values of and , which are determined according to the information given in the truth table of function *F*_{1}. The dotted lines in Fig 8 denote the candidate arcs filtered based on Remark 2. The solid line implies a selected arc among these candidate arcs. Note that the arc selection follows the MCT gate-network conversion procedure of Algorithm 1 because *C*^{2} *NOT*(2, 3;1) gate *G*_{1} and *C*^{1} *NOT*(3;2) gate *G*_{2} are given. The total network cost, i.e., the quantum cost, is 6 because *c*(*G*_{1}) = 5 and *c*(*G*_{2}) = 1, according to Table 3. The commodity labels on the arcs of Fig 8 show that each flow is delivered to the appropriate destination through the selected arcs, while satisfying the upper bound constraints for each arc and the demand constraint of the terminal node.

**Example 6**. Fig 9 describes the MCNF representation of the QRCS problem when an incompletely specified function *F*_{2} with *N*_{Q} = 3 and *N*_{D} = 2 is given. Thus, the network is constructed using three stages, each composed of eight state nodes. The truth table of function *F*_{2} is given in Table 5. The function *F*_{2} is generated by masking a part of the bits in the output states of function *F*_{1} with the unspecified bits. The three types of states, i.e., - - 0, - - 1, and - - -, are the output column of the truth table. Therefore, three distinct types of commodities, *k* = 1, 2, 3, originate from the source node *S*. The correspondence between the commodity index *k* and the output strings is presented in the column of Table 5. Table 5 also includes the values of and determined based on the given truth table of function *F*_{2}. As shown in of Table 5, the more varied way to send a flow to the terminal node *T* exists in the case of *F*_{2} because *F*_{2} is an incompletely specified function. However, note that the given feasible circuit is identical to Example 5; thus, the following result of the arc selection and network costs are the same. The commodity label on each of the arcs shows that all commodities are delivered to the appropriate destination while satisfying the upper bound constraints for each arc and the demand constraints of the terminal node.

### Mathematical model

This section proposes the whole optimization model for solving the QRCS problem described in the preceding sections. The sets and parameters in the proposed model are listed in Table 6, whereas the decision variables and their corresponding definitions are listed in Table 7. The model imposes a total of 14 types of variables to construct the model. Moreover, a total of 30 types of constraints were developed to describe the QRCS problem. (6a) (6b) (6c) (6d) (6e) (6f) (6g) (6h) (6i) (6j) (6k) (6l) (6m) (6n) (6o) (6p) (6q) (6r) (6s) (6t) (6u) (6v) (6w) (6x) (6y) (6z) (6aa) (6ab) (6ac) (6ad) (6ae)

Eq (6a) is an objective function of the model that minimizes a sum of the quantum cost of the decided MCT circuit. From a network optimization perspective, the objective function implies minimizing the total network cost, which is charged according to the subset of arcs in each gate level. Eqs (6b)–(6h) are the constraints that determine the network structure. In particular, Eqs (6b)–(6g) are constraints based on the MCNF model. In addition, Eqs (6b) and (6c) define the commodity constraint respectively on the initial stage and output level. Eq (6b) defines the initial input commodity of each inflow from the source node. The initial flows are already decided as parameters according to the target output in the given truth table. Eq (6c) defines the total demand of inflow for each commodity received at the terminal node. Eqs (6d) and (6e) are the conservation constraints of the flow for the nodes in the stages. In addition, Eqs (6f) and (6g) are the bundle constraints for the arcs in the gate and output levels, respectively. Because the network represents the permutation, Eq (6h) forces the symmetry in the arcs of each gate level.

Eqs (6i)–(6p) are constraints related to the generation of the circuit and gates. Eq (6i) implies that the control and target bits cannot be assigned to the same location of the circuit. By Eq (6j), if an MCT gate is assigned to a gate level, the gate must include a target bit. Eq (6k) assigns the MCT gate on the consecutive gate levels because, in some cases, not all levels are filled with gates. Eqs (6l)–(6n) sum the number of control bits for each gate. Eqs (6o) and (6p) suppress the assignment of control bits to the circuit if a gate is not assigned to the corresponding level.

Eqs (6q)–(6t) are preliminary constraints for the gate classification and the sync test. In addition, Eqs (6q) and (6r) express the sync test of the MCT gate, Eq (6s) defines the auxiliary variable for *CASE 3*, and Eq (6t) allows the CBS to pass the sync test when the corresponding gate does not contain the control bit.

Eqs (6u)–(6ac) are constraints that embody the MCT gate-network conversion described in Algorithm 1. Eq (6u) determines the arcs at the gate level when the gate is not assigned, which is denoted as *CASE 1*. In this case, every state node forms an arc with the state node that has an identical node label. Eqs (6v) and (6w) work jointly to determine the arcs of the gate level when a NOT gate is assigned, which is denoted as *CASE 2*. Eqs (6x) and (6y) are either-or constraints that discriminate *CASE 2* with two types of variables, i.e., *ν*^{d}, indicating that a gate is assigned to a gate level, and *u*^{d}, indicating that a control bit is contained in the assigned gate. Eqs (6z)–(6ab) are the constraints determining the arcs of the gate level in *CASE 3A*. Conversely, Eq (6ac) is a constraint that determines the arcs of the gate level in *CASE 3B*. Eqs (6ab) and (6ae) are the either-or constraints that discriminate *CASE 3A* and *CASE 3B* using two types of variables, i.e., *u*^{d}, indicating if an assigned gate contains the control bit, and , indicating if a CBS passes the sync test of the gate.

## Results

In this section, we provide details of the computational experiments on the proposed optimization model. The optimization model proposed in the previous section was implemented and compiled using Python 3.6.6. The experiment was conducted using Windows 10 OS on a personal computing with a 3.20-GHz Intel Core^{™} i7-8700U CPU with 16.00 GB of memory. The problems were solved by using Gurobi 9.0.0, and the maximum calculation time was set to 36,000s. If the optimal solution was not found within the maximum calculation time, the best feasible solution found was printed. All other parameters were set to their default values. The computational experiments on the proposed model used 44 Boolean reversible functions obtained from revlib [52]. Among the benchmark data, including up to 6 qubits, we used data commonly applied in previous studies.

The computational experiments were conducted by varying the values of *N*_{D} from 1 to 8. Table 8 compares the computational result of *N*_{D} = 7 with the results of prior studies in terms of quantum costs. In the last column of Table 8, Δ, the percentage of change in quantum cost for the solution to the case of *N*_{D} = 7 by the proposed model is compared to the best solution among the previous studies. The positive value in column Δ column implies that the proposed model derives a solution with an improved quantum cost compared to the best results among the previous studies.

For 23 cases out of a total of 44 functions, the circuit showed an improvement in terms of the quantum costs. The improvement ratio was a minimum 18.8% to a maximum of 68.6%. For 18 cases, our model obtained the same result as the previous studies regarding the quantum costs. Some cases showed an optimality gap of 0.0%, which indicates that the obtained solution is optimal in terms of the quantum costs. This implies that the proposed model can evaluate the computational performance of the proposed circuit synthesis heuristics. Case No. 9 *mod5d2* failed to find a feasible solution within the time limit from the remaining three cases. The other two cases showed a higher quantum cost than the previous results. For No. 37, *4mod7_v0*, the optimality gap appeared to be 84.6% even with the maximum computation time. Thus, we expect that a longer computation time is required to reach the same or better computational result than in previous studies. However, in case No. 44, *4mod5_v1*, we derived the optimal circuit of quantum cost 9, which is composed of five MCT gates from the proposed model. Thus, we carefully presume that there appears to be an error in the previous result. Overall, the computational result shows that the proposed methodology significantly improves the quantum costs.

Table 9 shows the full computational result of the proposed model. As *N*_{D} and *N*_{Q} increase, more nodes are explored when searching for the feasible or optimal solution. Accordingly, the required computational time also increases. As noted in Table 9, the total quantum cost tends to decrease as *N*_{D} increases in many cases. However, in some cases with *N*_{D} = 8, the optimality gap is insufficiently reduced within the time limit, resulting in a solution with a slightly higher quantum cost than in the case of *N*_{D} = 7. These cases have lower quantum costs than even the cases = of *N*_{D} ≤ 5.

Fig 10 visualizes the tendency of quantum costs varying with *N*_{D}. Each plot shows the change in quantum costs as *N*_{D} increases from 5 to 8. The vertical axis indicates the normalized value of quantum costs compared to the best solution among *N*_{D} ≤ 5. The number on the top-left of each plot indicates the data index from Table 9. The plots with black lines imply that no change in quantum costs occurred in the corresponding case. Conversely, the plot with blue lines shows the decrease in the quantum costs as *N*_{D} increases. However, note that among some of these cases, the quantum cost slightly increases in *N*_{D} = 8 cases because the optimality gap is not sufficiently narrowed within the limited computational time.

The number on the top-left of each plot indicates the data index in Table 9.

The improvement in the quantum costs is also shown in the resulting circuit. Figs 11–18 show the solution obtained in a circuit composed of MCT gates. The four circuits in Figs 11–14 are the result of No. 18 *mini_alu*, whereas the circuits in Figs 15–18 denote the circuit implementing the function No. 26 *4gt4_v1*. As mentioned in Section 2, the more control bits an MCT gate includes, the higher the quantum cost that is required to implement the gate physically. In Fig 11, the circuit is composed of five *C*^{2} *NOT* gates. However, in the following Figs 12–14, the number of *C*^{2} *NOT* gates decreases, and *CNOT* gates are used instead. The same trend is also shown in Figs 15–18. Although the *C*^{3} *NOT* gate is shown in Fig 15, the circuits in Figs 16–18 are composed of *CNOT* and *C*^{2} *NOT* gates. Thus, quantum costs decrease as the value of *N*_{D} increases in both cases.

## Discussions

We propose a network-based optimization model that synthesizes an optimal cost circuit for frequently used Boolean reversible functions in quantum computing. Notably, the optimization model for the QRCS problem appears uniquely as an extended form of the MCNF model that charges the network cost according to the subset of arcs selected. We also present experimental results based on benchmark data. In particular, comparing the experimental results with prior studies, we obtain improved solutions in terms of quantum cost for almost all of our data. The improvements in quantum costs have occurred from a minimum of 18.8% to a maximum of 68.6%.

The two main contributions of our research are as follows. First, our work suggests a novel research perspective to both a mathematical optimization and the quantum computing field. From a mathematical optimization perspective, this study proposes an exciting application of optimization to the practical problems arising from this new technical field. In addition, the optimization-based approach enhances the robustness and practicality of a quantum reversible circuit synthesis from the perspective of quantum computing. We introduce a realistic objective function that minimizes the number of fundamental quantum gates required when implementing Boolean reversible functions. Our approach can also be utilized to evaluate the heuristic algorithms fora circuit synthesis because the optimality of the solution is guaranteed. The optimal Boolean reversible circuits developed through the proposed model can also be used as building blocks for the later synthesis of large-size reversible circuits.

Second, we propose a new expansion of the MCNF model that uniquely appears in the QRCS problem. In contrast to the conventional MCNF model that charges the network cost per arc, the extended version sets the network cost according to the selected subset of arcs in each level. The proposed model also shows significantly better experimental results regarding both the solution quality, computational time, and optimality gap. Owing to the increased tractability of the newly proposed model, we conducted experiments within a broader range of the maximum number of gates. The results empirically show that the overall quantum cost required to implement a Boolean reversible circuit decreases when a larger number of MCT gates are used.

However, the experimental results show that when the size of the problem increases, the optimality gap does not sufficiently narrow within maximum calculation time. Therefore, follow-up research is underway to develop an optimization methodology that can handle large-scale problems. We have initiated this research by selecting an optimization methodology suitable for the proposed model structure. Furthermore, to efficiently solve the model, studies on heuristic algorithms are being planned. Future research on an extended MCNF model is also required and is expected to have potential applicability to various other conventional problems such as distribution and time-stage network problems, among others.

## References

- 1. Nielsen MA, Chuang IL. Quantum computation and quantum information. Phys Today. 2001;54(2):60.
- 2. Kielpinski D, Monroe C, Wineland DJ. Architecture for a large-scale ion-trap quantum computer. Nature. 2002;417(6890):709–711.
- 3. Monroe C, Raussendorf R, Ruthven A, Brown K, Maunz P, Duan LM, et al. Large-scale modular quantum-computer architecture with atomic memory and photonic interconnects. Physical Review A. 2014;89(2):022317.
- 4.
Grover LK. Fast quantum mechanical algorithm for database search In: Proceedings of the 28th annual ACM Symposium on Theory of Computing; 1996. p. 212–219.
- 5.
Shor PW. Algorithms for quantum computation: Discrete logarithms and factoring. In: Proceedings 35th Annual Symposium on Foundations of Computer Science. IEEE; 1994. p. 124–134.
- 6. Harrow AW, Hassidim A, Lloyd S. Quantum algorithm for linear systems of equations. Phys Rev Lett. 2009;103:150502.
- 7. Malossini A, Blanzieri E, Calarco T. Quantum genetic optimization. IEEE Trans Evol Comput. 2008;12(2):231–241.
- 8. Rebentrost P, Mohseni M, Lloyd S. Quantum support vector machine for big data classification. Phys Review Lett. 2014;113(13):130503.
- 9. Lloyd S, Mohseni M, Rebentrost P. Quantum principal component analysis. Nature Physics. 2014;10(9):631–633.
- 10. Cárdenas-López FA, Lamata L, Retamal JC, Solano E. Multiqubit and multilevel quantum reinforcement learning with quantum technologies. PloS One. 2018;13(7):e0200455.
- 11. Terry JP, Akrobotu PD, Negre CF, Mniszewski SM. Quantum isomer search. Plos one. 2020;15(1):e0226787.
- 12. Sergioli G, Giuntini R, Freytes H. A new quantum approach to binary classification. PloS One. 2019;14(5):e0216224.
- 13. Zurek WH. Decoherence, einselection, and the quantum origins of the classical. Rev Mod Phys. 2003;75(3):715.
- 14. Saeedi M, Markov IL. Synthesis and optimization of reversible circuits—a survey. ACM Computing Surveys (CSUR). 2013;45(2):1–34.
- 15. Barenco A, Bennett CH, Cleve R, DiVincenzo DP, Margolus N, Shor P, et al. Elementary gates for quantum computation. Physical Review A. 1995;52(5):3457. pmid:9912645
- 16.
Shende VV, Markov IL. CNOT-cost of TOFFOLI gates arXiv preprint arXiv:08032316. 2008;.
- 17.
Miller DM, Maslov D, Dueck GW. A transformation based algorithm for reversible logic synthesis. In: Proceedings of the 40th annual Design Automation Conference; 2003. p. 318–323.
- 18. Golubitsky O, Maslov D. A study of optimal 4-bit reversible Toffoli circuits and their synthesis. IEEE Transactions on Computers. 2011;61(9):1341–1353.
- 19.
Szyprowski M, Kerntopf P. Reducing quantum cost in reversible Toffoli circuits. arXiv preprint arXiv:11055831. 2011.
- 20. Prasad AK, Shende VV, Markov IL, Hayes JP, Patel KN. Data structures and algorithms for simplifying reversible circuits. ACM Journal on Emerging Technologies in Computing Systems (JETC). 2006;2(4):277–293.
- 21. Saeedi M, Zamani MS, Sedighi M, Sasanian Z. Reversible circuit synthesis using a cycle-based approach. ACM Journal on Emerging Technologies in Computing Systems (JETC). 2010;6(4):1–26.
- 22. Zhu W, Li Z, Zhang G, Pan S, Zhang W. A reversible logical circuit synthesis algorithm based on decomposition of cycle representations of permutations. International Journal of Theoretical Physics. 2018;57(8):2466–2474.
- 23.
Agrawal A, Jha NK. Synthesis of reversible logic. In: Proceedings Design, Automation and Test in Europe Conference and Exhibition. vol. 2. IEEE; 2004. p. 1384–1385.
- 24. Gupta P, Agrawal A, Jha NK. An algorithm for synthesis of reversible logic circuits. IEEE Trans Comput-Aided Design Integr Circuits Syst. 2006;25(11):2317–2330.
- 25. Bandyopadhyay C, Parekh S, Rahaman H. Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits. IET Computers & Digital Techniques. 2018;12(4):167–175.
- 26.
Wille R, Drechsler R. BDD-based synthesis of reversible logic for large functions. In: Proceedings of the 46th Annual Design Automation Conference; 2009. p. 270–275.
- 27. Lee J, Ye YH, Huang X, Yang RL. Binary-decision-diagram-based decomposition of Boolean functions into reversible logic elements. Theoretical Computer Science. 2020;814:120–134.
- 28. Hawash A, Awad A, Abdalhaq B. Reversible Circuit Synthesis Time Reduction Based on Subtree-Circuit Mapping. Applied Sciences. 2020;10(12):4147.
- 29. Stojković S, Stanković R, Moraga C, Stanković M. Reversible Circuits Synthesis from Functional Decision Diagrams by using Node Dependency Matrices. Journal of Circuits, Systems and Computers. 2020;29(05):2050079.
- 30.
Datta K, Rathi G, Sengupta I, Rahaman H. Synthesis of reversible circuits using heuristic search method. In: 2012 25th International Conference on VLSI Design. IEEE; 2012. p. 328–333.
- 31. Maslov D, Dueck GW, Miller DM. Techniques for the synthesis of reversible Toffoli networks. ACM Transactions on Design Automation of Electronic Systems (TODAES). 2007;12(4):42–es.
- 32. Maslov D, Dueck GW, Miller DM, Negrevergne C. Quantum circuit simplification and level compaction. IEEE Trans Comput-Aided Design Integr Circuits Syst. 2008;27(3):436–444.
- 33.
Wille R, Saeedi M, Drechsler R. Synthesis of reversible functions beyond gate count and quantum cost. arXiv preprint arXiv:10044609. 2010.
- 34. Hirata Y, Nakanishi M, Yamashita S, Nakashima Y. An efficient conversion of quantum circuits to a linear nearest neighbor architecture. Quantum Inf Comput. 2011;11(1):142.
- 35. Große D, Wille R, Dueck GW, Drechsler R. Exact multiple-control Toffoli network synthesis with SAT techniques. IEEE Trans Comput-Aided Design Integr Circuits Syst. 2009;28(5):703–715.
- 36. Sasamal TN, Singh AK, Mohan A. Reversible logic circuit synthesis and optimization using adaptive genetic algorithm. Procedia Computer Science. 2015;70:407–413.
- 37. Abubakar MY, Jung LT, Zakaria N, Younes A, Abdel-Aty AH. Reversible circuit synthesis by genetic programming using dynamic gate libraries. Quantum Inf Process. 2017;16(6):160.
- 38. Jung J, Choi IC. Reversible logic circuit synthesis for quantum computing via a gate pattern-based optimization model. Journal of the Korean Institute of Industrial Engineers. 2020;46(4):421–431.
- 39. Wang IL. Multi-commodity network flows: A survey, Part I: Applications and Formulations. International Journal of Operations Research. 2018;15(4):145–153.
- 40. Ford LR Jr, Fulkerson DR. A suggested computation for maximal multi-commodity network flows. Management Sci. 1958;5(1):97–101.
- 41. Benders JF. Partitioning procedures for solving mixed-variables programming problems. Computational Management Science. 2005;2(1):3–19.
- 42. Dantzig GB, Wolfe P. The decomposition algorithm for linear programs. Econometrica: Journal of the Econometric Society. 1961; p. 767–778.
- 43. Cappanera P, Frangioni A. Symmetric and asymmetric parallelization of a cost-decomposition algorithm for multi-commodity flow problems. INFORMS J Comput. 2003;15(4):369–384.
- 44. Frangioni A, Manca A. A computational study of cost reoptimization for min-cost flow problems. INFORMS J Comput. 2006;18(1):61–70.
- 45. Brotcorne L, Labbé M, Marcotte P, Savard G. A bilevel model for toll optimization on a multi-commodity transportation network. Transp Sci. 2001;35(4):345–358.
- 46. Cappanera P, Gallo G. A multi-commodity flow approach to the crew rostering problem. Oper Res. 2004;52(4):583–596.
- 47. Brown GG, Graves GW, Honczarenko MD. Design and operation of a multi-commodity production/distribution system using primal goal decomposition. Management Sci. 1987;33(11):1469–1480.
- 48. Khan MH. Cost Reduction in Nearest Neighbour Based Synthesis of Quantum Boolean Circuits. Engineering Letters. 2008;16(1).
- 49.
Sasamal T, Gaur H, Singh A, Mohan A. Reversible circuit synthesis using evolutionary algorithms. In: Design and Testing of Reversible Logic. Springer; 2020. p. 115–128.
- 50. Figgatt C, Maslov D, Landsman K, Linke NM, Debnath S, Monroe C. Complete 3-Qubit Grover search on a programmable quantum computer. Nature communications. 2017;8(1):1–9.
- 51. Kashefi E, Kent A, Vedral V, Banaszek K. Comparison of quantum oracles. Physical Review A. 2002;65(5):050304.
- 52.
Wille R, Große D, Teuber L, Dueck GW, Drechsler R. RevLib: An online resource for reversible functions and reversible circuits. In: Int’l Symp. on Multi-Valued Logic; 2008. p. 220–225.
- 53. Maslov D, Dueck GW, Miller DM. Toffoli network synthesis with templates. IEEE Trans on CAD. 2005;24(6):807–817.
- 54.
Wille R, Große D. Fast Exact Toffoli Network Synthesis of Reversible Logic. In: Int’l Conf. on CAD; 2007. p. 60–64.
- 55.
Wille R, Le HM, Dueck GW, Große D. Quantified Synthesis of Reversible Logic. In: Design, Automation and Test in Europe; 2008. p. 1015–1020.