Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.


Introduction
In the modern lives, the computing power of digital devices has been improved by the technology innovations in the miniaturisation of semiconductor transistors [1]. The famous Moore's Law will soon experience its fundamental limit because of various constraints in bulk silicon (Si) technology, especially in the sub-10-nm atomic scales [2][3][4]. Therefore, the more-than-Moore development of the alternative field-effect transistors (FETs) has attracted much attention in the nanoelectronic research communities. Numerous industrial and public funds and programmes were initiated globally to overcome these "roadblocks" for long-terms advances in computing technology beyond Moore's Law [5].
Among the options in the more-than-Moore race, two-dimensional (2D) materials have emerged as the prospective contenders owing to their atomically thin structure. Following the success of graphene since 2004 [6], research activities regarding 2D materials are intensely stimulated. Until now, more than 1800 exfoliable 2D candidates are theoretically predicted based on density-functional theory (DFT) [7], among which silicene could play a major role in future transistors owing to its outstanding carrier mobility [8]  cutting-edge Si wafer technology [9]. Silicene was also shortlisted as a potential material for transistor miniaturisation in the International Roadmap for Devices and Systems (IRDS) [10]. In 2015, Tao et al. [9] fabricated the first silicene-based transistor operating at room temperature. Moreover, silicene nanosheets have successfully been fabricated on various substrates in their buckled [11][12][13] and planar [14] forms. However, the deposition of silicene monolayers on metals substrates is less practical viable for transistor applications, as compared to the direct growth on insulating layers, such as dielectrics or oxides [15]. This shortcoming can be addressed by using computational modelling and simulation while waiting for the breakthrough in silicene-based fabrication techniques.
Concerning the computational models of silicene-based transistors [16,17], rigorous efforts were invested by many groups of researchers. The absence of bandgap in pristine silicene did not halt its exploration for nanotransistor applications. In spite of the challenges, various bandgap engineering techniques have been explored, and such examples include confinement through silicene nanoribbons (SiNRs) [18][19][20], co-decoration [21], and doping [22][23][24]. Among the aforementioned techniques, doping is the most commonly employed technique in the semiconductor industry to alter the electronic properties [25]. Furthermore, the performance of SiNR FETs are sensitive to their device dimensions [20,26]; and it is still a major challenge to precisely control the widths of nanoribbons even for the established graphene monolayers [27]. Therefore, a uniformly aluminium (Al) doped silicene monolayer was proposed to engineer the bandgap of silicene, producing the AlSi 3 monolayer. In addition, a SPICE-compatible model was created to facilitate studies beyond the device-level simulation [28], such as the gate and logic levels. Fig 1 shows the schematic diagrams of the proposed AlSi 3 FET and the simplified topof-the-barrier (ToB) nanotransistor circuit model. In this study, we developed of a SPICEcompatible model for the proposed AlSi 3 FET from the ToB nanotransistor model and benchmarked its device performance metrics with other published low-dimensional transistor models. Section 2 describes the modelling procedures to obtain the current-voltage (I-V) characteristics and the respective model evaluation methodology. Section 3 discusses the device performance of AlSi 3 FET with respect to its close low-dimensional contenders. Finally, Section 4 includes the conclusion of this work and future work recommendation.

Methodology
This section describes the overall modelling procedures employed in this study, where the overall flowchart is shown in Fig 2.

ToB nanotransistor and SPICE models
The atomic structure of the AlSi 3 monolayer (as shown in Fig 1) was adapted from published DFT study [29]. By using the derivation from time-independent Schrödinger equation [30], the electronic transport effective mass was then obtained by using nearest neighbour tightbinding (NNTB) model and parabolic band assumptions as m � e ¼ 0:235m 0 and m � h ¼ 0:255m 0 for electrons and holes, respectively. The material-level modelling was shown in details in our previous work [22]. Table 1 summarises the device parameters of the AlSi 3 FETs. In the ToB nanotransistor model [31], net induced mobile charge can be obtained by ΔP = (P S +P D )−P 0 where P S and P D are the non-equilibrium charge densities at the source and drain terminals, respectively, and P 0 is the equilibrium charge density. The self-consistent potential U SCF at the ToB is obtained by using where q is the constant for electric charge and the total terminal capacitances is expressed as C S = C G +C D +C S . Because the source terminal is always set to be zero, α S can be ignored. In an ideal FET, the perfect gate and drain control parameters α G = 1 and α D = 0 [18] are used to mimic the ideal I-V characteristics. However, the default gate and drain control parameters α G = 0.880 and α D = 0.035 [31] were used in this work. Subsequently, the current-voltage (I-V) characteristics of p-type AlSi 3 FET can be obtained in terms of V DS and V GS , by employing Landauer-Büttiker ballistic transport equation [31] along with Fermi-Dirac integral solutions [32], given as

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Device performances analysis of p-doped silicene-based field effect transistor using SPICE-compatible model with the normalised energies of for source and drain, respectively. In the equations, g is the degeneracy factor (set as 2 to include up and down spins); ℏ is the Planck's constant; and k B is the Boltzmann constant. Fig  3(A) shows the I-V characteristics for AlSi 3 FET produced by the ToB nanotransistor model. Following that, the results from ToB nanotransistor were further used to create the SPICE model to allow cross-platform and non-iterative simulation. Moreover, SPICE models are one of the essential tools in the IC design industry for simulation [28]. Before creating the SPICE model, a non-linear regression model [33] was employed to fit the self-consistent potential

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Device performances analysis of p-doped silicene-based field effect transistor using SPICE-compatible model U SCF , given as where the coefficients P {j}{k−j} for each respective |V GS | j |V DS | k−j term were computed and optimised using MATLAB curve fitting tool. By using the MATLAB Curve Fitting tool, it was found that the lower orders of polynomial equations fail to fit the USCF well and, as a result, are unable to reproduce accurate I-V characteristics. Therefore, the fifth-order polynomial equation (highest number of order available in the MATLAB Curve Fitting tool) is chosen

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Device performances analysis of p-doped silicene-based field effect transistor using SPICE-compatible model although the resulting equation is slightly long. The expansion of Eq (5) and the respective coefficients P {j}{k−j} are attached along with the SPICE model library files in the S1 File. Fig 3  (B) shows the I-V characteristics for AlSi 3 FET produced by the SPICE model.

Model evaluation
In this subsection, a statistical method is employed to evaluate the accuracy of the SPICE model with respect to the ToB nanotransistor model for the proposed AlSi 3 FET. The models were evaluated by using the normalised root-mean-square-deviations (RMSD) [29], given as

RMSD ¼
ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi where N denotes the total number of data, p i and q i are the values of i th data for the ToB nanotransistor model and the SPICE model, respectively. Fig 4(A) shows the I-V characteristics

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Device performances analysis of p-doped silicene-based field effect transistor using SPICE-compatible model combining the results of the ToB nanotransistor model and the SPICE model. The point-bypoint differences to compute RMSD are plotted in Fig 4(B). Overall, 0.91% of RMSD is produced by the SPICE model when it is benchmarked with the results from the ToB nanotransistor model, indicating that the model has produced a decent fit.

Performances analysis and discussion
We can analyse the device performances by extracting the device metrics from the proposed ptype AlSi 3 FET model. Fig 5 shows the graphical extraction approach to obtain on-to-off current (I on /I off ) ratio, subthreshold swing (SS), and drain-induced barrier lowering (DIBL). The proposed AlSi 3 FET produces an I on /I off ratio of 2.6×10 5 , a SS of 67.8 mV/dec, and a DIBL of 48.2 mV/V. In this work, we compared our proposed p-type AlSi 3 FET with respect to other low-dimensional FETs. We have selected other published works on low-dimensional FETs to fairly assess the device performance of the proposed AlSi 3 FET. The selected published models include codecorated SiNR FET [21], 27-ASiNR FET [20], Si nanowire (SiNW) FET [34], Si thin sheet FET [35], carbon nanotube (CNT) FET [36], graphene nanoribbon (GNR) FET [37], black phosphorene (BP) FET [38], and monolayer molybdenum disulfide (MoS 2 ) FET [39]. To concisely compare the device performance metrics, the comparisons are presented as bar graphs as shown in Fig 6. Regarding the I on /I off ratio, the performance of AlSi 3 FET model is slightly inferior to 27-ASiNR FET [20] and MoS 2 FET [39]. Regarding the SS, AlSi 3 FET model is also slightly higher than the 27-ASiNR FET [20]. Concerning the DIBL, AlSi 3 FET model is also outperformed by 27-ASiNR FET [20] and CNT FET [36]. However, the challenges remain owing to the fabrication compatibility of non-Si-based materials and the difficulty to precisely control the widths of nanoribbons [27,40]. Therefore, the proposed AlSi 3 FET model is still a prospective alternative for future nanotransistor applications.

Conclusion
In this paper, we have investigated a SPICE-compatible model for p-type uniformly Al-doped silicene FET. Following that, the device performance of the proposed model is compared with

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Device performances analysis of p-doped silicene-based field effect transistor using SPICE-compatible model other published low-dimensional nanotransistors. Although the proposed silicene FET is slightly inferior to a few competitors, silicene-based FETs are still one of the potential ways for more-than-Moore nanoelectronic applications owing to its Si-based nature. This work can be extended by performing further circuit-level simulation beyond the transistor device level by using the proposed SPICE model.