Histogram-Based Calibration Method for Pipeline ADCs

Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based method requires a large volume of data and a long test duration, especially for a high resolution ADC. A fast and accurate calibration method for pipelined ADCs is proposed in this research. The proposed calibration method composes histograms through the outputs of each stage and calculates error sources. The digitized outputs of a stage are influenced directly by the operation of the prior stage, so the results of the histogram provide the information of errors in the prior stage. The composed histograms reduce the required samples and thus calibration time being implemented by simple modules. For 14-bit resolution pipelined ADC, the measured maximum integral non-linearity (INL) is improved from 6.78 to 0.52 LSB, and the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are improved from 67.0 to 106.2dB and from 65.6 to 84.8dB, respectively.


Introduction
Analog-to-digital converters (ADCs) which perform signal transfers between the analog and digital domains are considered as the most important devices in systems-on-chips (SoCs) [1]- [3]. ADCs have been widely used in applications such as communications, energy, healthcare, instrumentation and measurement, automotive, aerospace, and so on. Generally, ADCs are the largest bottleneck in the process of data transmission, indicating that an exact operation should be guaranteed. Especially, when they are used in healthcare SoCs or hybrid electronic vehicles [4,5], a minor malfunction can cause a fatal accident. In addition, as the clock speed of SoCs increases in 3D-ICs including TSVs(Through-Silicon Vias), ADCs with the higher speed have been required. For these reasons, calibration methods for accuracy and specification have been applied in many ADCs.
Since pipelined ADCs can operate with high-speed and high-resolution simultaneously, they are widely used in the domain that successive approximation ADCs and time-interleaving ADCs cannot cover [6]. However, pipelined ADCs inevitably include capacitor mismatch and finite op-amp gain in each stage due to their structure, which generates a non-linearity error so that a calibration technique is required for improved performance [7,8]. The digital calibration technique needs less power and less hardware overhead and improves performance more as CMOS technology improves, so they have been researched in many studies [8]- [13].
Previous digital calibration methods have measured the non-linearity characteristic of the error sources that occur in multiplying DACs (MDACs) and have applied the inverse transfer function to it. In [8], an interpolation-based calibration method is introduced to compensate both linear and nonlinear errors from pipeline stages. In this method, a parallel calibration ADC channel is used to prevent the propagation of errors. It has an advantage that requires little calibration overhead and short convergence time. However, the calibration technique in [8] has too complex procedures to get the optimal solution. The calibration method proposed in [9] improves the linearity of two-step ADC by simultaneously subtracting switch feedthrough, op-amp offset and inter-stage gain from the digital outputs. This method can be implemented simply using only some extra digital logic, which does not influence the original structure. However, it does not consider the finite op-amp gain errors which seriously impact on the performance of pipelined ADCs. The background calibration method described in [13] estimates the inter-stage gain of each stage by conventional foreground calibration technique. An initial estimation of inter-stage gain is conducted in foreground, and then the gain variations due to temperature and voltage are tracked in background. This previous method has an advantage of short calibration time but low accuracy of calibration results is a weakness.
In this research, a histogram-based digital calibration technique for pipelined ADCs is proposed. The proposed method targets capacitor mismatches and finite op-amp gain errors of MDACs in each pipeline stage. To reduce the calibration time without the loss of performance, it generates stage-histograms through the digitized outputs of each stage and calibrates the errors by analyzing the histograms. The stage-histograms and additional calibration modules can be implemented with low hardware overhead. After the proposed calibration method, significant linearity improvements can be obtained with fewer calibration times compared with the previous methods.

Background
The general structure of a 1.5-bit/stage pipelined ADC is shown in Fig 1 [14]. As described in Fig 1, a pipelined ADC includes front-end S/H circuits and N stages arranged in series. Each stage consists of an S/H circuit, sub-ADC, sub-DAC, subtractor, and gain stage. The output (V i ) of the previous stage goes through the S/H circuits and the sub-ADC generating the pipeline stage outputs. Simultaneously, the residues are produced through the sub-DAC, subtractor, and gain stage and delivered to the next stage. The outputs occurring at each stage are stored in the pipeline latches and go through the DEC circuits. After traversing the DEC circuits, the final outputs are determined, eliminating some errors. The DEC circuits perform digital correction using multiple bits occurring at each stage. The multi-bit pipeline stages reward some comparator offset errors by setting the '01' stage between output '00' and '10' compared to single-bit pipelined stages that generate an output of '0' or '1' at each stage. The threshold voltage is generally set to ±1/4 V ref , and the more accurate outputs can then be obtained.

Method
Error analysis on inter-stages A notation table to summarize the following key variables is shown in Table 1. The proposed calibration method composes stage-histograms using the outputs of each stage and determines the error sources by analyzing these histograms. The proposed calibration method targets nonlinearity errors due to capacitor mismatches and finite op-amp gains of MDACs.   the distribution of the outputs that occur in the process of digitizing through the sub-ADC of the next stage. The transfer function at the i th stage, including the capacitor mismatch (E cm i ) and gain error (E gain i ), is decided as shown in (1). In this research, the proposed method is explained based on a 1.5-bit/stage pipelined ADC, but it can be applied in another multiple-bit/ stage structure, using the same principle.
The digitized outputs of the (i+1) th stage(D i+1 ) are influenced by the operation of i th stage, so the results of (i+1) th histogram reflects the errors in i th stage. The effects of E cm i and E gain i are derived by the collected histogram data. To determine the effects of inserted errors on histograms, the range of each outputs in the next stage are calculated. The transition points, where the output values change, can be obtained by measuring x when substituting v ref /4 for y in (1). Fig 3 shows the output ranges on the transfer curve including non-linearity errors.
The length of each section where the values of 00, 01, and 10 in the next stage are calculated and the results are expressed as (2). We assume that the input distribution of each stage is uniform. From (2), a capacitor mismatch which raises or lowers the outputs can be determined by the difference between the 10 and 00 probability values (p(D i+1 = 10) from p(D i+1 = 00)). In addition, a gain error changes the slope of the output transfer curve of the next stage, which can be calculated through the probability of the 01 value that occurs in the next stage. The determining error sources can be written as (3). The α in (3)   rate, input range. The calculated error sources are applied to the calibrated outputs during the DEC process for eliminating non-linearities.
Flow and structure of the histogram-based calibration The flow chart of the proposed calibration is shown in Fig 4. The proposed method creates the stage-histograms and collects the fault information of each stage. When the enough samples are applied, the errors can be calculated by mathematical analysis above mentioned. The proposed calibration technique executes the propagation error elimination for more accurate  The proposed calibration architecture has an advantage to have low complexity in digital hardware. Since the stage-histograms are composed at each stage, the proposed method has significantly less area overhead than the conventional histogram method. The conventional histogram requires 2 N histogram data to distinguish the all cases of N-bit ADC [15], but the proposed method needs only 3N histogram data. The stage-histogram consists of several gates and counters to distinguish the 00, 01, and 10 values. The error source register in DEC also needs low area overhead because the compensation data are produced by the combination of the error sources in each stage.

Results and Discussion
MATLAB and C++ simulations were performed to prove the performance of the proposed calibration method. The simulations were performed on 14-bit pipelined ADCs with parameters in Table 2. The simulations were performed repetitively according to the various errors, and the maximum values were measured. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) results before and after calibration are described in S1 File and      To measure the area overhead caused by the proposed calibration method, Synopsys's DesignVision was used to compile and synthesize the Verilog design. Fig 10 shows the synthesis results of the calibration circuits. From the provided area report, we can conclude that they require about 800 NAND gate counts. Compared with [8] which requires 912 gates only for decoders, the proposed method has the lower area overhead. Table 3 shows the comparison between the proposed method and previous works. In the performance improvement, based on INL and SFDR, the proposed calibration method improves the performance from 6.78 to 0.52 LSB and from 65.6 to 84.8dB, respectively. Compared with [13] which improves SFDR from 69 to 85dB, the proposed method is more efficient in the calibration of non-linearity. In case of calibration time, [13] requires 2 million samples for 12-bit ADC and the proposed method requires 16 million samples for 14-bit ADC. Considering the resolution of ADC, the required calibration times can be considered as almost the same. Compared with [8], the proposed method shows performance enhancement on the same level as [8], but the low complexity of the hardware is the advantage of the proposed method compared with [8].

Conclusions
This paper proposes a digital calibration method for pipelined ADCs based on stage-histogram data. The proposed calibration calculates the error sources in each stage by analyzing the stagehistogram and eliminates their effects in DEC circuits. Generating the histograms in each stage enables the accurate measurement of error sources, so the calibration time can be reduced. The implementation of the proposed method requires about 800 gate counts, which means the low hardware overhead compared with the previous works. In addition, it includes only digital process, so it does not modify the analog design of the ADCs. After calibration, the measured maximum INL is improved from 6.78 to 0.52 LSB, and the SFDR and SNDR are improved from 67.0 to 106.2dB and from 65.6 to 84.8dB, respectively.   Table 3. Comparison with the previous works. J.Yuan [8]