Fig 1.
Typical structure of artificial intelligence accelerator with systolic-based array.
Fig 2.
Example of pattern generation in local binary pattern algorithm.
Fig 3.
Block diagram of previous and proposed PE designs.
(a) previous LBP and min–max circuits; (b) proposed PE with optimized data-processing circuits and test block.
Fig 4.
Block diagram of proposed optimized data-processing circuits.
Table 1.
Input control decisions of the input controller.
Fig 5.
Block diagram of proposed module with data-processing circuit for error detection and test block.
Fig 6.
Test-bench results for functional validation of proposed data-processing circuit.
(a) LBP mode; (b) min–max mode.
Table 2.
Hardware size measured at the equivalent gate count of the 2-input NAND gate.
Fig 7.
Power consumption of previous and proposed modules after FPGA implementation.
Fig 8.
Design view of previous and proposed modules.
(a) LBP and min–max circuits; (b) optimized data-processing circuit.
Fig 9.
Results of fault-injection experiments.
Number of faults affecting outputs in (a) LBP experiments and (b) min–max experiments.
Fig 10.
AFVs from fault-injection experiments.
(a) LBP experiments; (b) min–max experiments.
Table 3.
Test coverage of proposed module for PE input registers.